Incorporating silicon atoms into a metal oxide gate dielectric using gas cluster ion beam implantation

• US 5,907,780 A
• Filed: 06/17/1998
• Issued: 05/25/1999
• Est. Priority Date: 06/17/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gardner, Mark I., Gilmer, Mark C.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Thompson, Craig
• Application Number:
  US09/098,704
• Time in Patent Office: 342 Days
• Field of Search: 438/299, 438/197, 438/144, 438/158, 438/167
• US Class Current: 438/299
• CPC Class Codes: H01J 2237/0812 Ionized cluster beam [ICB] sources
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

An integrated circuit fabrication process is provided for forming silicon dioxide in the vacancies of a gate dielectric comprising metal oxide. The gate dielectric has a relatively high dielectric constant to promote high capacitive coupling between two conductive layers separated by the gate dielectric. The gate dielectric may be used in, e.g., a MOS transistor device or an EEPROM memory cell. The silicon dioxide is formed within the gate dielectric by first incorporating silicon atoms within the gate dielectric using gas cluster ion beam implantation. Gas cluster ion beam implantation affords shallow implantation of the silicon atoms. The gate dielectric is then annealed in a diffusion furnace while being exposed to a steam- or oxygen-bearing ambient. As a result of being heated, Si atoms react with O atoms to form SiO₂ which fills oxygen vacancies in the gate dielectric. Absent the oxygen vacancies, the gate dielectric is less likely to allow current to leak between the two conductive layers. The SiO₂ serves to terminate dangling bonds within the gate dielectric so that hot carriers and foreign species are substantially inhibited from being trapped within the gate dielectric.

Claims

1. A method for forming an integrated circuit, comprising:

forming a metal oxide layer above a semiconductor substrate;

supercooling a gas comprising silicon atoms to form a cluster of silicon atoms; and

implanting the cluster of silicon atoms into the metal oxide layer.

2. The method of claim 1, wherein the metal oxide layer comprises a dielectric selected from the group consisting of tantalum pentoxide, titanium oxide, zirconium oxide, barium titanate, barium zirconate, barium tungstate, magnesium dioxide, strontium niobate, tungsten trioxide, zinc tungstate, yttrium sesqeioxide, strontium tungstate, and strontium titanate.

3. The method of claim 1, further comprising annealing the metal oxide layer while exposing it to steam or oxygen to form silicon oxide within the metal oxide layer.

4. The method of claim 1, wherein said supercooling a gas comprises passing the gas through a nozzle into a vacuum region of less than about 100 milliTorr.

5. The method of claim 1, wherein said implanting the cluster of silicon atoms comprises:

ionizing the cluster of silicon atoms; and

accelerating the cluster of silicon atoms in an electric field such that the cluster of silicon atoms are forwarded to the metal oxide layer.

6. The method of claim 5, wherein the cluster of silicon atoms separate into individual silicon atoms which share a total energy of the cluster of silicon atoms when the cluster of silicon atoms pass into the metal oxide layer.

7. The method of claim 1, further comprising depositing silicon nitride across the semiconductor substrate prior to said forming a metal oxide layer.

8. The method of claim 7, wherein the metal oxide layer comprises a thickness of approximately 40 to 60 Å

, and wherein the silicon atoms are implanted to a depth of approximately 25 to 30 Å

below an upper surface of the metal oxide layer.

9. The method of claim 1, further comprising depositing a gate conductor across the metal oxide layer subsequent to said forming a metal oxide layer.

10. The method of claim 9, wherein the gate conductor comprises a material selected from the group consisting of polysilicon, iridium, tungsten, and tungsten nitride.

11. The method of claim 9, further comprising etching away select portions of the metal oxide layer and the gate conductor from the semiconductor substrate.

12. The method of claim 11, further comprising:

implanting a first concentration of dopant into areas of the semiconductor substrate exclusive of underneath the gate conductor to form lightly doped drain areas therein;

forming a pair of dielectric spacers extending laterally from opposed sidewall surfaces of the gate dielectric; and

implanting a second concentration of dopant substantially greater than the first concentration of dopant into source and drain regions of the semiconductor substrate spaced laterally from the gate dielectric by the pair of dielectric spacers.

13. The method of claim 12, wherein the pair of dielectric spacers comprise silicon nitride.

14. The method of claim 1, further comprising:

forming a tunnel dielectric across the semiconductor substrate; and

depositing a first gate conductor across the tunnel dielectric prior to said forming a metal oxide layer above a semiconductor substrate.

15. The method of claim 14, further comprising:

depositing a second gate conductor across the metal oxide layer subsequent to said forming a metal oxide layer;

etching select portions of the tunnel dielectric, the first gate conductor, the metal oxide layer, and the second gate conductor to expose source and drain regions of the semiconductor substrate; and

implant dopant species into the source and drain regions.