Radio communication analyzer having collective measurement function of transmission test items

• US 5,907,797 A
• Filed: 03/20/1997
• Issued: 05/25/1999
• Est. Priority Date: 03/28/1996
• Status: Expired due to Fees

• Current Assignee: Anritsu Corporation
• Original Assignee: Anritsu Corporation
• Inventors: Morikawa, Takayuki, Hanatatsu, Masami, Tagawa, Chihiro
• Primary Examiner(s): Bost, Dwayne D.
• Assistant Examiner(s): SCOTT, LINWOOD
• Application Number:
  US08/821,768
• Time in Patent Office: 796 Days
• Field of Search: 455/115, 455/63, 455/61, 455/60, 455/42, 455/67.1, 455/67.3, 379/88, 375/316, 375/322, 375/354
• US Class Current: 455/115.2
• CPC Class Codes: H04B 17/104 of other parameters, e.g. DC offset, delay or propagation times
• CPC Class Codes: H04B 17/16 Test equipment located at the transmitter

Abstract

A radio communication analyzer tests the signal characteristics of a carrier, as a target signal to be tested, which has undergone quadrature modulation using a digital data signal output from a radio unit to be tested. A quadrature demodulation section performs quadrature demodulation of the target signal and outputs a baseband signal. A storage section stores the waveform data of the baseband signal. A clock synchronous detection section detects clock synchronization information contained in the target signal based on the waveform data. A demodulation section sequentially reads out the waveform data and obtains demodulated digital data in accordance with the clock synchronization information. A burst synchronous detection section generates burst synchronization information representing a burst start position of the target signal on the basis of the demodulated digital data or the waveform data.

Claims

1. A radio communication analyzer for testing signal characteristics of a carrier, as a target signal to be tested, which has undergone quadrature modulation using a digital data signal output from a radio unit to be tested, comprising:

an A/D converter for converting the target signal into a target digital signal;

a quadrature demodulation section for performing quadrature demodulation of the digital signal obtained by said A/D converter and outputting digital baseband signals;

a waveform memory for storing waveforms of the digital baseband signals output from said quadrature demodulation section;

a clock synchronous detection section for detecting clock synchronization information for the digital data signal which is contained in the target signal from the signal waveforms stored in said waveform memory;

a demodulation section for sequentially reading out the baseband signals stored in said waveform memory and obtaining demodulated digital data by using the clock synchronization information detected by said clock synchronous detection section;

a burst synchronous detection section for producing burst synchronization information representing a burst start position of the target signal from the demodulated digital data produced by said demodulation section or the signal waveforms stored in said waveform memory;

I/Q coordinate data measuring means for measuring characteristics of an inphase component (I) and a quadrature component (Q) of the target signal, on an I/Q coordinate system, from the signal waveforms stored in said waveform memory by using the clock synchronization information, the burst synchronization information, and the demodulated digital data;

power measuring means for obtaining an amplitude domain characteristic of the target signal from the signal waveforms stored in said waveform memory by using the clock synchronization information and the burst synchronization information;

frequency measuring means for obtaining a frequency domain characteristic of the target signal from the signal waveforms stored in said waveform memory by using the burst synchronization information; and

a display unit for simultaneously displaying at least two of the characteristics of the inphase component (I) and quadrature component (Q) of the target signal which are obtained by said I/Q coordinate data measurement means, the amplitude domain characteristic of the target signal which is obtained by said power measuring means, and the frequency domain characteristic of the target signal which is obtained by said frequency measuring means.

2. An analyzer according to claim 1, wherein the characteristics of the inphase component (I) and quadrature component (Q) of the target signal which are measured by said I/Q coordinate measuring means on the I/Q coordinate system include a modulation precision and frequency deviation of the target signal.

3. An analyzer according to claim 1, wherein the amplitude domain characteristic of the target signal which is measured by said power measuring means includes an antenna power deviation, carrier-off interval leakage power, and ramp-up/ramp-down characteristics of the target signal.

4. An analyzer according to claim 1, wherein the frequency domain characteristic of the target signal which is measured by said frequency measuring means includes an occupied bandwidth and adjacent channel leakage power of the target signal.

5. An analyzer according to claim 1, wherein the characteristics of the inphase component (I) and quadrature component (Q) of the target signal which are measured by said I/Q coordinate measuring means on the I/Q coordinate system include a modulation precision and frequency deviation of the target signal,

the amplitude domain characteristic of the target signal which is measured by said power measuring means includes an antenna power deviation, carrier-off interval leakage power, and ramp-up/ramp-down characteristics of the target signal, and

the frequency domain characteristic of the target signal which is measured by said frequency measuring means includes an occupied bandwidth and adjacent channel leakage power of the target signal.

6. An analyzer according to claim 1, wherein said quadrature demodulation section comprises:

a reference signal generating section using a ROM storing sine waveform data, amplitude values stored at addresses in the ROM being sequentially read out to finally output a reference signal having a frequency equal to a predetermined intermediate frequency;

a first multiplying section to which the target signal is input and the reference signal from said reference signal generating section is directly input; and

a second multiplying section to which the target signal is input and the reference signal from said reference signal generating section is input after undergoing a π

/2 phase shift, and

said first and second multiplying sections multiply the input target signals by the two orthogonal reference signals to output baseband signals I(t) and Q(t) of the inphase component (I) and the quadrature component (Q) of the target signal as quadrature demodulated outputs.

7. An analyzer according to claim 6, wherein said clock synchronous detection section regenerates a clock signal serving as clock synchronization information for regenerating data contained in the target signal from the baseband signals I(t) and Q(t) output from said first and second multiplying sections.

8. An analyzer according to claim 7, wherein said demodulation section comprises:

first and second sampling sections for sampling the baseband signals I(t) and Q(t) output from said first and second multiplying sections in synchronism with the clock signal regenerated by said clock synchronous detection section; and

a demodulator for generating the demodulated digital data from two sampling data output from said first and second sampling sections.

9. An analyzer according to claim 6, wherein said clock synchronous detection section comprises:

first and second square calculating sections for squaring the baseband signals I(t) and Q(t) output from said first and second multiplying sections;

a synthesizing section for synthesizing two outputs from said first and second square calculating sections and outputting a synthetic signal;

a reference clock generating section using a ROM storing sine waveform data, amplitude values stored at addresses in the ROM being sequentially read out to finally output a reference clock signal having a frequency substantially equal to a clock frequency equal to a period of an original signal;

a third multiplying section to which the synthetic signal output from said synthesizing section is input and the reference clock signal from said reference clock generating section is directly input;

a fourth multiplying section to which the synthetic signal output from said synthesizing section is input and the reference clock signal from said reference clock generating section is input after undergoing a π

/2 phase shift,

said third and fourth multiplying sections outputting phase signals I₂ (t) and Q₂ (t) by multiplying the input synthetic signals by the two orthogonal reference clock signals;

first and second low-pass filters for outputting integral values i and q by removing high-frequency components from the phase signals I₂ (t) and Q₂ (t) output from said third and fourth multiplying sections;

a phase difference calculating section for calculating a phase difference ψ

=Tan^-1 (q/i) between the baseband signals I(t) and Q(t) and the reference clock signals from the integral values i and q output from said first and second low-pass filters; and

a timing calculating section for outputting a predetermined clock signal as clock synchronization information for the digital data signal when a phase of a reference phase of the reference clock signal output from said reference clock generating section is reached with the ψ

in accordance with the phase difference ψ

=Tan^-1 (q/i) output from said phase difference calculating section.

10. An analyzer according to claim 1, wherein said quadrature demodulation section comprises:

a reference signal generating section using a ROM storing sine waveform data, amplitude values stored at addresses in the ROM being sequentially read out to finally output a reference signal having a frequency equal to a predetermined intermediate frequency;

a first multiplying section to which the target signal is input and the reference signal from said reference signal generating section is directly input; and

a second multiplying section to which the target signal is input and the reference signal from said reference signal generating section is input after undergoing a π

/2 phase shift,

said first and second multiplying sections multiply the input target signals by the two orthogonal reference signals to output baseband signals I(t) and Q(t) of the inphase component (I) and the quadrature component (Q) of the target signal as quadrature demodulated outputs,

said clock synchronous detection section regenerates a clock signal serving as clock synchronization information for regenerating data contained in the target signal from the baseband signals I(t) and Q(t) output from said first and second multiplying sections,

said demodulation section comprises;

first and second sampling sections for sampling the baseband signals I(t) and Q(t) output from said first and second multiplying sections in synchronism with the clock signal regenerated by said clock synchronous detection section; and

a demodulator for generating the demodulated digital data from two sampling data output from said first and second sampling sections, and

said clock synchronous detection section comprises;

first and second square calculating sections for squaring the baseband signals I(t) and Q(t) output from said first and second multiplying sections;

a synthesizing section for synthesizing two outputs from said first and second square calculating sections and outputting a synthetic signal;

a reference clock generating section using a ROM storing sine waveform data, amplitude values stored at addresses in the ROM being sequentially read out to finally output a reference clock signal having a frequency substantially equal to a clock frequency equal to a period of an original signal;

a third multiplying section to which the synthetic signal output from said synthesizing section is input and the reference clock signal from said reference clock generating section is directly input;

a fourth multiplying section to which the synthetic signal output from said synthesizing section is input and the reference clock signal from said reference clock generating section is input after undergoing a π

/2 phase shift,

said third and fourth multiplying sections outputting phase signals I₂ (t) and Q₂ (t) by multiplying the input synthetic signals by the two orthogonal reference clock signals;

first and second low-pass filters for outputting integral values i and q by removing high-frequency components from the phase signals I₂ (t) and Q₂ (t) output from said third and fourth multiplying sections;

a phase difference calculating section for calculating a phase difference ψ

=Tan^-1 (q/i) between the baseband signals I(t) and Q(t) and the reference clock signals from the integral values i and q output from said first and second low-pass filters; and

a timing calculating section for outputting a predetermined clock signal as clock synchronization information for the digital data signal when a phase of a reference phase of the reference clock signal output from said reference clock generating section is reached with the ψ

in accordance with the phase difference ψ

=Tan^-1 (q/i) output from said phase difference calculating section.

11. A radio communication analyzer for testing signal characteristics of a carrier, as a target signal to be tested, which has undergone quadrature modulation using a digital data signal output from a radio unit to be tested, comprising:

quadrature demodulation means for performing quadrature demodulation of the target signal and outputting a baseband signal;

storage means for storing waveform data of the baseband signal output from said quadrature demodulation means;

clock synchronous detection means for detecting clock synchronization information contained in the target signal on the basis of the waveform data stored in said storage means;

demodulation means for sequentially reading out the waveform data stored in said storage means and obtaining demodulated digital data in accordance with the clock synchronization information detected by said clock synchronous detection means;

burst synchronous detection means for producing burst synchronization information representing a burst start position of the target signal based on the demodulated digital data produced by said demodulation means or the waveform data stored in said storage means;

measuring means for measuring an amplitude domain characteristic of the target signal, a frequency domain characteristic of the target signal, and characteristics of an inphase component (I) and quadrature component (Q) of the target signal on an I/Q coordinate system, based on the waveform data stored in said storage means, by selectively using the clock synchronization information detected by said clock synchronous detection means, the burst synchronization information detected by said burst synchronous detection means, and the demodulated digital data obtained by said demodulation means; and

output means for outputting the amplitude domain characteristic of the target signal, the frequency domain characteristic of the target signal, and the characteristics of the inphase component (I) and quadrature component (Q) of the target signal on the I/Q coordinate system, which are obtained by said measuring means, in association with each other.

12. An analyzer according to claim 11, wherein the characteristics of the inphase component (I) and quadrature component (Q) of the target signal which are measured by said measuring means on the I/Q coordinate system include a modulation precision and frequency deviation of the target signal.

13. An analyzer according to claim 11, wherein the amplitude domain characteristic of the target signal which is measured by said measuring means includes an antenna power deviation, carrier-off interval leakage power, and ramp-up/ramp-down characteristics of the target signal.

14. An analyzer according to claim 11, wherein the frequency domain characteristic of the target signal which is measured by said measuring means includes an occupied bandwidth and adjacent channel leakage power of the target signal.

15. An analyzer according to claim 11, wherein the characteristics of the inphase component (I) and quadrature component (Q) of the target signal which are measured by said measuring means on the I/Q coordinate system include a modulation precision and frequency deviation of the target signal,

the amplitude domain characteristic of the target signal which is measured by said measuring means includes an antenna power deviation, carrier-off interval leakage power, and ramp-up/ramp-down characteristics of the target signal,

the frequency domain characteristic of the target signal which is measured by said measuring means includes an occupied bandwidth and adjacent channel leakage power of the target signal, and

said output means includes a display unit for simultaneously displaying at least two of the inphase component (I) and quadrature component (Q) of the target signal, the amplitude domain characteristic of the target signal, and the frequency domain characteristic of the target signal, which are obtained by said measuring means.

16. An analyzer according to claim 11, wherein said quadrature demodulation section comprises:

a reference signal generating section using a ROM storing sine waveform data, amplitude values stored at addresses in the ROM being sequentially read out to finally output a reference signal having a frequency equal to a predetermined intermediate frequency;

a first multiplying section to which the target signal is input and the reference signal from said reference signal generating section is directly input; and

a second multiplying section to which the target signal is input and the reference signal from said reference signal generating section is input after undergoing a π

/2 phase shift, and

said first and second multiplying sections multiply the input target signals by the two orthogonal reference signals to output baseband signals I(t) and Q(t) of the inphase component (I) and the quadrature component (Q) of the target signal as quadrature demodulated outputs.

17. An analyzer according to claim 16, wherein said clock synchronous detection section regenerates a clock signal serving as clock synchronization information for regenerating data contained in the target signal from the baseband signals I(t) and Q(t) output from said first and second multiplying sections.

18. An analyzer according to claim 17, wherein said demodulation section comprises:

first and second sampling sections for sampling the baseband signals I(t) and Q(t) output from said first and second multiplying sections in synchronism with the clock signal regenerated by said clock synchronous detection section; and

a demodulator for decoding producing the demodulated digital data from two sampling data output from said first and second sampling sections.

19. An analyzer according to claim 16, wherein said clock synchronous detection section comprises:

first and second square calculating sections for squaring the baseband signals I(t) and Q(t) output from said first and second multiplying sections;

a synthesizing section for synthesizing two outputs from said first and second square calculating sections and outputting a synthetic signal;

a reference clock generating section using a ROM storing sine waveform data, amplitude values stored at addresses in the ROM being sequentially read out to finally output a reference clock signal having a frequency substantially equal to a clock frequency equal to a period of an original signal;

a third multiplying section to which the synthetic signal output from said synthesizing section is input and the reference clock signal from said reference clock generating section is directly input;

a fourth multiplying section to which the synthetic signal output from said synthesizing section is input and the reference clock signal from said reference clock generating section is input after undergoing a π

/2 phase shift,

said third and fourth multiplying sections outputting phase signals I₂ (t) and Q₂ (t) by multiplying the input synthetic signals by the two orthogonal reference clock signals;

first and second low-pass filters for outputting integral values i and q by removing high-frequency components from the phase signals I₂ (t) and Q₂ (t) output from said third and fourth multiplying sections;

a phase difference calculating section for calculating a phase difference ψ

=Tan^-1 (q/i) between the baseband signals I(t) and Q(t) and the reference clock signals from the integral values i and q output from said first and second low-pass filters; and

a timing calculating section for outputting a predetermined clock signal as clock synchronization information for the digital data signal when a phase of a reference phase of the reference clock signal output from said reference clock generating section is reached with the ψ

in accordance with the phase difference ψ

=Tan^-1 (q/i) output from said phase difference calculating section.

20. An analyzer according to claim 11, wherein said quadrature demodulation section comprises:

a reference signal generating section which is constituted by a ROM in which sine waveform data is stored, and sequentially reads out amplitude values stored at addresses in the ROM to finally output a reference signal having a frequency equal to a predetermined intermediate frequency;

a first multiplying section to which the target signal is input and the reference signal from said reference signal generating section is directly input; and

a second multiplying section to which the target signal is input and the reference signal from said reference signal generating section is input after undergoing a π

/2 phase shift,

said first and second multiplying sections multiply the input target signals by the two orthogonal reference signals to output baseband signals I(t) and Q(t) of the inphase component (I) and the quadrature component (Q) of the target signal as quadrature demodulated outputs,

said clock synchronous detection section regenerates a clock signal serving as clock synchronization information for regenerating data contained in the target signal from the baseband signals I(t) and Q(t) output from said first and second multiplying sections,

said demodulation section comprises;

first and second sampling sections for sampling the baseband signals I(t) and Q(t) output from said first and second multiplying sections in synchronism with the clock signal regenerated by said clock synchronous detection section; and

a demodulator for producing the demodulated digital data from two sampling data output from said first and second sampling sections into four decoded data by parallel/serial conversion, and

said clock synchronous detection section comprises;

first and second square calculating sections for squaring the baseband signals I(t) and Q(t) output from said first and second multiplying sections;

a synthesizing section for synthesizing two outputs from said first and second square calculating sections and outputting a synthetic signal;

a reference clock generating section which is constituted by a ROM in which sine waveform data is stored, and sequentially reads out amplitude values stored at addresses in the ROM to finally output a reference clock signal having a frequency substantially equal to a clock frequency equal to a period of an original signal;

a third multiplying section to which the synthetic signal output from said synthesizing section is input and the reference clock signal from said reference clock generating section is directly input;

a fourth multiplying section to which the synthetic signal output from said synthesizing section is input and the reference clock signal from said reference clock generating section is input after undergoing a π

/2 phase shift,

said third and fourth multiplying sections outputting phase signal I₂ (t) and Q₂ (t) by multiplying the input synthetic signals by the two orthogonal reference clock signals;

first and second low-pass filters for outputting integral values i and q by removing high-frequency components from the phase signals I₂ (t) and Q₂ (t) output from said third and fourth multiplying sections;

a phase difference calculating section for calculating a phase difference ψ

=Tan^-1 (q/i) between the baseband signals I(t) and Q(t) and the reference clock signals from the integral values i and q output from said first and second low-pass filters; and

a timing calculating section for outputting a predetermined clock signal as clock synchronization information for the digital data signal when a phase of a reference phase of the reference clock signal output from said reference clock generating section in accordance with the phase difference ψ

=Tan^-1 (q/i) output from said phase difference calculating section.