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Memory control unit using preloaded values to generate optimal timing of memory control sequences between different memory segments

  • US 5,907,863 A
  • Filed: 08/16/1996
  • Issued: 05/25/1999
  • Est. Priority Date: 08/16/1996
  • Status: Expired due to Term
First Claim
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1. A programmable memory controller comprising:

  • a complementary pair of memory control segments, A and B coupled to receive overlapping requests for access to a corresponding complementary memory segment;

    each said control segment having individual sets of address and control lines coupled to one of a corresponding pair of complementary segments;

    a common data bus shared by said control segments coupled to said complementary memory segments;

    a plurality of allow mode signal generators within each of said control segments A and B coupled to receive said overlapping request for access; and

    each allow mode signal generator providing programmed delayed or non-delayed allow mode signals coupled to start an overlapping sequence of operations in the other of said control segments B or A.

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