Memory control unit using preloaded values to generate optimal timing of memory control sequences between different memory segments
First Claim
1. A programmable memory controller comprising:
- a complementary pair of memory control segments, A and B coupled to receive overlapping requests for access to a corresponding complementary memory segment;
each said control segment having individual sets of address and control lines coupled to one of a corresponding pair of complementary segments;
a common data bus shared by said control segments coupled to said complementary memory segments;
a plurality of allow mode signal generators within each of said control segments A and B coupled to receive said overlapping request for access; and
each allow mode signal generator providing programmed delayed or non-delayed allow mode signals coupled to start an overlapping sequence of operations in the other of said control segments B or A.
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Accused Products
Abstract
A memory controller is described that comprises individual control segments for controlling memory that is divided into individual pairs of memory segments. The programmable memory controller provides improved average access times for memory devices by reducing the number of wait cycles between memory operations. A common data bus is shared between the memory segments. However, each control segment provides individual sets of address and control lines to each memory segment so that control sequences can occur simultaneously between multiple control and memory segments. Accordingly, when a control sequence is in process within one segment, another control sequence can occur simultaneously in another segment. By overlapping control sequences in this fashion, the bandwidth of the data bus is increased by remaining idle less frequently. Each control segment comprises a plurality of synchronous countdown register timers. Each countdown register is loaded with a programmable value at the beginning of a control sequence within its control segment. The programmable value is subsequently decremented by a value of one (`counts down`) upon each pulse of a system clock. Each counter counts down to a value of zero and then holds that value until another memory sequence begins in the control segment. A value of zero within a counter indicates to the other control segment(s) that a particular control sequence therein can begin.
17 Citations
19 Claims
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1. A programmable memory controller comprising:
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a complementary pair of memory control segments, A and B coupled to receive overlapping requests for access to a corresponding complementary memory segment;
each said control segment having individual sets of address and control lines coupled to one of a corresponding pair of complementary segments;a common data bus shared by said control segments coupled to said complementary memory segments; a plurality of allow mode signal generators within each of said control segments A and B coupled to receive said overlapping request for access; and each allow mode signal generator providing programmed delayed or non-delayed allow mode signals coupled to start an overlapping sequence of operations in the other of said control segments B or A. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A programmable memory controller comprising:
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complementary control segments each coupled to control a memory device having multiple segments; each control segments having individual control and address lines coupled to one of said memory segments, and a plurality of allow mode signal generators within each said control segments, each generator having a plurality of programmable values, wherein each programmable value defines when a particular control sequence is allowed to begin in the other of said complementary control segments. - View Dependent Claims (9, 10)
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11. A programmable memory controller comprising:
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a complementary pair of memory segments coupled to receive overlapping memory request comprising first and second control segments; said first control segment being coupled to a first memory segment via a first set of address and control lines; said first control segment comprising programmable allow signal generation means for generating first allow control sequence signals; said second control segments being coupled to a second memory segment via a second set of address and control lines, and providing overlapping control sequences to said second memory segments according to said second memory segments according to said allow control sequence signals from said first control segment. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification