Semiconductor device fabrication

• US 5,908,312 A
• Filed: 05/28/1997
• Issued: 06/01/1999
• Est. Priority Date: 05/07/1996
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Hillenius, Steven James, Ma, Yi, Liu, Chun-Ting, Roy, Pradip Kumar, Cheung, Kin Ping
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Hack, Jonathan
• Application Number:
  US08/864,220
• Time in Patent Office: 734 Days
• Field of Search: 438/287, 438/766, 438/770, 438/786
• US Class Current: 438/287
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/2822 with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A method of preventing diffusion penetration of the dopant used to dope polysilicon gate material in a MOSFET is disclosed. Atomic nitrogen is introduced into the substrate prior to gate oxide growth. The nitrogen later diffuses upward into the gate oxide and blocks subsequent ion implanted gate dopants from penetrating to the substrate. Low dosages of atomic nitrogen implantation, while not significantly affecting gate oxide growth rate, produce significant improvements in the damage immunity of thin gate oxides.

Claims

1. A method of semiconductor integrated circuit fabrication comprising:

embedding atomic nitrogen into a substrate such that said atomic nitrogen extends to a top surface of said substrate;

forming a dielectric layer upon said substrate after said embedding step;

forming a material layer upon said dielectric layer;

exposing said material layer to a dopant species;

patterning said material layer to form a gate.

2. The method of claim 1 in which said embedding step includes ion implantation.

3. The method of claim 2 in which said embedding step includes ion implantation which is performed at an energy between 5 KeV and 50 KeV and at a dose between 10¹³ /cm² and 5×

10¹⁴ /cm².

4. The method of claim 1 in which said material layer is polysilicon.

5. The method of claim 1 in which said dopant species is boron.

6. The method of claim 1 in which said dielectric is thermally grown silicon dioxide.

7. The method of claim 6 in which said dielectric is formed by exposing said substrate to oxygen at a temperature between 700°

C. and 1000°

C.

8. The method of claim 1 in which the thickness of said dielectric is between 10 Å

and 200 Å

.

9. The method of claim 1 in which the thickness of said material layer is between 500Å

and 3000Å

.

10. The method of claim 1 in which said dielectric is formed by exposing said substrate to an atmosphere of N₂ O.

11. The method of claim 10 in which said exposure occurs at a temperature between 800 and 900°

C.

12. The method of claim 3 in which the dose is about 1×

10¹⁴ /cm² to about 5×

10¹⁴ /cm².