Data transfer network on a chip utilizing a multiple traffic circle topology

• US 5,908,468 A
• Filed: 10/24/1997
• Issued: 06/01/1999
• Est. Priority Date: 10/24/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hartmann, Alfred C.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/957,093
• Time in Patent Office: 585 Days
• Field of Search: 395/311, 395/280, 395/281, 395/800.01, 395/200.8, 395/308
• US Class Current: 710/316
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses

Abstract

A computer chip includes a plurality of modules interconnected in an on-chip data transfer network configured in a circular topology to form preferably a plurality of traffic circles. The various modules may be processors, memories and/or hybrids and may include, or be coupled through, a communications port coupled to one of the buses such that the communications port is operable to transmit and receive data on one of the buses. Each of the communications ports is operable to route data from a source bus to a destination bus. The traffic circles are formed by groups of communications ports, and buses or groups of transfer paths. The buses may be operable to transfer data in only one direction or in two directions. The transfer of data on the buses by the modules may be controlled by an on-chip bus controller coupled to one or more of the buses. The bus controller may also include arbiter logic for arbitrating access to one or more of the plurality of buses. One or more of the plurality of communications ports may be further operable to transfer data from one of the buses to a bus connection operable to route data to a device external to computer chip. One or more of the plurality of buses includes addressing and control lines.

Claims

1. A computer chip comprising a data transfer network, the data transfer network comprising:

a plurality of buses comprised on the computer chip, wherein each of said plurality of buses is configured in a circular topology;

a plurality of communications ports comprised on the computer chip, wherein each of said plurality of communications ports is coupled to one or more of said plurality of buses, wherein one or more of said plurality of communications ports is operable to route data from a source bus to a destination bus; and

a plurality of modules, wherein each of said plurality of modules is coupled to at least one of said plurality of communications ports, wherein said plurality of modules are operable to communicate with each other through one or more of said buses.

2. The computer chip of claim 1, wherein each of said plurality of buses is operable to transfer data in only one direction.

3. The computer chip of claim 2, wherein said plurality of buses include a first bus and a second bus, wherein the first bus is operable to transfer data in a first direction and wherein the second bus is operable to transfer data in a second opposite direction.

4. The computer chip of claim 3, wherein each of said plurality of buses is operable to transfer data in a direction opposite to a direction of a nearest neighboring bus of said plurality of buses.

5. The computer chip of claim 1, wherein each of said plurality of buses are operable to transfer data in two directions.

6. The computer chip of claim 1, wherein said plurality of communications ports are further operable to route data from a first bus to an associated module.

7. The computer chip of claim 1, wherein said each of said plurality of modules is coupled to two or more communications ports of said plurality of communications ports.

8. The computer chip of claim 7, wherein each of said two or more communications ports is coupled to different buses of said plurality of buses.

9. The computer chip of claim 1, wherein each of said modules comprises one or more communications ports, wherein each of said one or more communications ports are coupled to ones of said plurality of buses, wherein said each of said one or more communications ports is operable to transmit and receive data on said ones of said plurality of buses.

10. The computer chip of claim 1, further comprising:

a bus controller comprised on said computer chip, wherein said bus controller is coupled to one or more of said plurality of buses, wherein said bus controller is operable to control data transfers by said plurality of modules on or through said one or more of said plurality of buses;

wherein the bus controller includes arbiter logic for arbitrating access to the one or more of said plurality of buses.

11. The computer chip of claim 1, wherein each of said plurality of modules is selected from a group including a processor, a memory, an I/O controller, a task-specific hybrid, and a task-general hybrid.

12. The computer chip of claim 1,

wherein one or more of said plurality of communications ports is further operable to transfer data from one of said plurality of buses to a bus connection operable to route said transferred data to a device off of said computer chip;

and

wherein one or more of said plurality of communications ports is further operable to receive data from said device off of said computer chip and transfer said received data to one of said plurality of buses.

13. The computer chip of claim 1, wherein one or more of said plurality of buses includes address and control lines.

14. A computer chip comprising a data transfer network, the data transfer network comprising:

a plurality of communications ports comprised on the computer chip;

a plurality of transfer paths comprised on the computer chip, wherein each of said plurality of transfer paths are directly connected between two of said communications ports, wherein a first group of said plurality of transfer paths and a first group of said plurality of communications ports collectively forms a first traffic circle, wherein a second group of said plurality of transfer paths and a second group of said plurality of communications ports collectively forms a second traffic circle different from said first traffic circle, wherein each of said plurality of communications ports is coupled to at least two transfer paths, wherein each of said plurality of communications ports is operable to route data from a source transfer path to a destination transfer path; and

a plurality of modules, wherein each of said plurality of modules is coupled to at least one of said plurality of communications ports, wherein said plurality of modules are operable to communicate with each other through said transfer paths.

15. The computer chip of claim 14, wherein at least a subset of said plurality of modules are coupled to one or more communications ports in said first group of said plurality of communications ports in said first traffic circle, wherein said subset of said plurality of modules are further coupled to one or more communications ports in said second group of said plurality of communications ports in said second traffic circle, wherein said subset of said plurality of modules are operable to communicate through said first traffic circle and said second traffic circle.

16. The computer chip of claim 14, wherein data flow on said second traffic circle is in the opposite direction to data flow on said first traffic circle.

17. The computer chip of claim 14, wherein each of said modules comprises a communications port coupled to one of said transfer paths, wherein the communications port is operable to transmit and receive data on said one of said transfer paths.

18. The computer chip of claim 14, wherein each of said plurality of transfer paths are operable to transfer data in two directions.

19. The system of claim 14, wherein each of said plurality of modules is selected from a group including a processor, a memory, an I/O controller, a task-specific hybrid, and a task-general hybrid.

20. A computer chip comprising a data transfer network, the data transfer network comprising:

a first circular bus comprised on the computer chip;

a second circular bus comprised on the computer chip;

wherein each of said first and second circular buses is configured in a circular topology, wherein each of said first and second circular buses is operable to transfer data in a circular fashion;

a plurality of communications ports comprised on the computer chip;

wherein each of said plurality of communications ports is coupled to one or more of said first circular data bus and said second circular data bus, wherein each of said plurality of communications ports is operable to route data from a source bus to a destination bus; and

a plurality of modules, wherein each of said plurality of modules is coupled to at least one of said plurality of communications ports, wherein said plurality of modules are operable to communicate with each other through one or more of said buses.