Integrated voltage regulator circuit with vertical transistor

• US 5,909,110 A
• Filed: 12/12/1997
• Issued: 06/01/1999
• Est. Priority Date: 12/17/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Taddiken, Albert H., Yang, Jau-Yuann, Yuan, Han-Tzong, Plumton, Donald L.
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US08/989,840
• Time in Patent Office: 536 Days
• Field of Search: 323/274, 323/282, 323/284
• US Class Current: 323/282
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence

Abstract

A voltage regulator (10) comprising a vertical channel transistor (12). The vertical channel transistor (12) may have a gate (16), a voltage input terminal (18), and a voltage output terminal (20). A reference voltage supply (14) may be coupled to the gate (16).

Claims

1. A voltage regulator, comprising:

a vertical channel transistor having a gate, a voltage input terminal, and a voltage output terminal; and

a reference voltage supply coupled to the gate.

2. The voltage regulator of claim 1, the reference voltage supply further comprising a voltage clamping device coupled to a ground and a resistive element coupled between a voltage supply and the voltage clamping device.

3. The voltage regulator of claim 1, the reference voltage supply further comprising a diode coupled to a ground and a resistive element coupled between a voltage supply and the diode.

4. The voltage regulator of claim 3, the resistive element further comprising a resistor.

5. The voltage regulator of claim 1, the reference voltage supply further comprising a diode coupled to a ground and a resistive element coupled between the voltage output terminal of the vertical channel transistor and the diode.

6. The voltage regulator of claim 1, the voltage input terminal further comprising a drain of the vertical channel transistor.

7. The voltage regulator of claim 1, the voltage output terminal further comprising a source of the vertical channel transistor.

8. An integrated circuit chip, comprising:

a vertical channel transistor formed on a semiconductor layer;

the vertical channel transistor having a gate, a voltage input terminal, and a voltage output terminal;

a reference voltage supply formed on the semiconductor layer; and

the reference voltage supply coupled to the gate.

9. The integrated circuit chip of claim 8, the reference voltage supply further comprising:

a voltage clamping device formed on the semiconductor layer;

the voltage clamping device coupled to a ground;

a resistive element formed on the semiconductor layer; and

the resistive element coupled between a voltage supply and the voltage clamping device.

10. The voltage regulator of claim 8, the reference voltage supply further comprising:

a diode formed on the semiconductor layer;

the diode coupled to a ground;

a resistive element formed on the semiconductor layer; and

the resistive element coupled between a voltage supply and the diode.

11. The voltage regulator of claim 8, the resistive element further comprising a resistor.

12. The voltage regulator of claim 8, the reference voltage supply further comprising:

a diode formed on the semiconductor layer;

the diode coupled to a ground;

a resistive element formed on the semiconductor layer; and

the resistive element coupled between the voltage output terminal of the vertical channel transistor and the diode.

13. The voltage regulator of claim 8, the voltage input terminal further comprising a drain of the vertical channel transistor.

14. The voltage regulator of claim 8, the voltage output terminal further comprising a source of the vertical channel transistor.

15. A method of regulating voltage, comprising:

receiving an input voltage at a voltage input terminal of a vertical channel transistor;

receiving an output voltage at a voltage output terminal of the vertical channel transistor;

supplying a reference voltage at a gate of the vertical channel transistor; and

in response to a voltage difference between the reference voltage at the gate and the output voltage at the voltage output terminal, adjusting with the gate a resistance between the voltage input terminal and the voltage output terminal to conform the output voltage at the voltage output terminal to the reference voltage at the gate.

16. The method of claim 15, wherein the voltage disparity is measured by a resistive element coupled between the gate and the voltage output terminal.

17. The method of claim 15, wherein the voltage disparity is measured by a resistor coupled between the gate and the voltage output terminal.

18. The method of claim 16, wherein the reference voltage is supplied to the gate by a voltage clamping device coupled to a ground and to the resistive element.

19. The method of claim 16, wherein the reference voltage is supplied to the gate by a series of diodes coupled to a ground and to the resistive element.

20. The method of claim 16, wherein the voltage input terminal is a drain of the vertical channel transistor and the voltage output terminal is a source of the vertical channel transistor.