Circuits with dynamically biased active loads

• US 5,909,127 A
• Filed: 02/14/1996
• Issued: 06/01/1999
• Est. Priority Date: 12/22/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reynolds, Scott Kevin, Pearson, Dale Jonathan
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/601,628
• Time in Patent Office: 1,203 Days
• Field of Search: 326/17, 326/83, 326/121, 326/115, 326/113, 326/31-34, 326/126-127, 327/313, 327/318, 327/323, 327/65, 327/67
• US Class Current: 326/115
• CPC Class Codes: H03K 19/0136 by means of a pull-up or down element
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 19/086 Emitter coupled logic
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/1738 using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]

Abstract

This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings. The output is sampled and maintained at near ideal bias voltage with a voltage follower type circuit which provides a gain of less than unity and finite delay. Particular circuit implementations using various semiconductor technologies are described and many others are possible. Although the invention may find primary use in VLSI logic circuits, especially those requiring high speed and low power, it is also shown to be useful in analog circuits. Alternate circuit configurations for dynamically biased active load devices are described.

Claims

1. A device comprising:

a plurality of I/O transistors, each I/O transistor having an I/O transistor input terminal being a device input adapted to receive a corresponding external signal, and an I/O transistor output terminal, at least one I/O transistor output terminal being a device output adapted to transmit a signal externally;

a plurality of active loads, each of said active loads having an active load input, each active load being coupled to a different I/O transistor output terminal and serving as an I/O transistor load of said different I/O transistor output terminal; and

a plurality of output sensing circuits, each output sensing circuit being coupled to a different one of said active loads, each output sensing circuit having a sensing input coupled to said different I/O transistor output terminal, a sensing output coupled to said active load input of said different one of said active loads, a voltage gain less than unity and a delay;

said sensing circuit providing negative feedback to said active load, and wherein an output signal at the device output swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and the external signal swings substantially from 1.4 to 1.1.

2. A device as in claim 1 wherein each said I/O transistor output terminal is a logical output of a logic circuit.

3. A device as in claim 2 wherein said logic circuit is a MOSFET CML type circuit.

4. A device as in claim 1 wherein said device is formed using bipolar semiconductor technology.

5. A device as in claim 1 wherein said sensing means provides a dynamic bias to said load input.

6. A device as in claim 1 wherein said sensing means is comprised of:

a sensing transistor having a sensing transistor supply terminal coupled to a first supply rail, a sensing transistor input terminal forming said sensing input, and a sensing transistor output terminal forming said sensing output; and

a sensing current source coupled between said sensing output and a second supply rail.

7. A device as in claim 6 wherein said sensing current source having a sensing current source input to accept a sensing bias.

8. A device as in claim 7 wherein said logic circuit having a differential amplifier configuration, and further comprised of an amplifier current source, said amplifier current source having an amplifier current source input to accept a logic bias.

9. A device as in claim 1 wherein said sensing circuit is comprised of:

a first transistor having a first transistor supply terminal coupled to a first supply rail;

a second transistors having a second transistor input terminal common with a first transistor input terminal of said first transistor and forming said sensing input, a second transistor output terminal common with a first transistor output terminal of said first transistor and forming said sensing output, and a second transistor supply terminal coupled to a second supply rail.

10. A device as in claim 9 wherein said first supply rail is at ground potential.

11. A device as in claim 2 wherein said logic circuit performs an AND/NAND logic function.

12. A device as in claim 2 wherein said logic circuit performs an OR/NOR logic function.

13. A device as in claim 2 wherein said logic circuit performs an inverting buffer logic function.

14. A device as in claim 2 wherein said logic circuit performs an XOR/XNOR logic function.

15. A device as in claim 2 wherein said logic circuit performs a logic function of a majority function gate.

16. A device as in claim 2 wherein said logic circuit performs a logic function of a master-slave flip flop.

17. A device as in claim 1 wherein said active load has a load bias current of less than 25 microamperes.

18. A device as in claim, 1 wherein the device is resistorless.

19. A device as in claim, 1 wherein the device output is a single inversion of the device input.

20. A logic gate comprising:

a plurality of active loads; and

a plurality of time-delayed negative feedback bias circuits, each of the bias circuits is coupled to a different one of said active loads, the logic gate having a plurality of logic gate inputs adapted to receive an external input signal and a plurality of logic gate outputs, at least one of said logic gate outputs being adapted to transmit an output signal externally, each of said active loads having no resistors and serving as a load to a different one of said logic gate outputs, and each said logic gate output having an output signal being a single inversion of the external input signal at said logic gate input and being delayed from the external signal by a propagation delay resulting from a single active component, and wherein

said bias circuit dynamically biasing said active load such that said active load presents an effective load that varies according to a logic state of said logic gate output, and wherein

an output signal at said at least one of said logic gate outputs swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and the external input signal swings substantially from 1.4 to 1.1.

21. A gate as in claim 20 wherein said active load becomes turned-on less strongly when said at least one output is in a high logic state, and becomes turned-on more strongly when said at least one output is in a low logic state.

22. A gate as in claim 20 wherein said bias circuit controls a logic swing of said output.

23. A gate as in claim 22 wherein said logic swing is between V_DD and (V_DD -300 mv).

24. A gate as in claim 21 wherein a transition time for changing between said high logic state and said low logic state is less than 200 ps.

25. A method for dynamically biasing each of a plurality of active loads within a device, said method comprising the steps of:

providing each of said active loads with a load input and a load output, said active loads being resistorless, said load output being coupled to a circuit output of said device, said circuit output being adapted to transmit an output signal externally, and having a signal with a signal level;

sensing said signal;

amplifying said signal level with a gain of less than unity;

delaying said signal to form a delayed output; and

feeding said delayed output to said load input to provide negative feedback to said at least one active load, and wherein

an output signal at the circuit output swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and a device input signal swings substantially from 1.4 to 1.1.

26. A method as in claim 25 wherein said circuit output is an output of a CML circuit.

27. A method as in claim 25 wherein said step of sensing is comprised of the steps of:

providing a transistor having a transistor supply terminal coupled to a first supply rail, a transistor input terminal forming a sensing input, a transistor output terminal forming said delayed output; and

providing a sensing current source coupled between said delayed output and a second supply rail.

28. A method as in claim 27 wherein said sensing current source having a sensing current source input to accept a sensing bias.

29. A method as in claim 26 wherein said CML circuit having a differential amplifier configuration, and is further comprised of an amplifier current source, said amplifier current source having an amplifier current source input to accept a logic bias.

30. A device comprising:

a plurality of transistors,

at least one input circuit element, each circuit element consisting of one of said transistors and having at least one device input adapted for receiving an external input signal and at least one device output adapted to provide an output signal, said device output having an output signal being a single inversion of the external input signal,

each circuit element having;

an active load coupled to said at least one device output, said active load having a load input, and

an output sensing circuit having a sensing input coupled to said at least one device output, a sensing output coupled to said load input, a voltage gain less than unity and a delay, said sensing circuit providing negative feedback to said active load, and wherein

an output signal at said at least one device output swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and a signal at said at least one device input swings substantially from 1.4 to 1.1.

31. A logical gate comprising:

a plurality of transistors;

at least one of said transistors having a first transistor node being a gate input node adapted to receive an external signal and a second transistor node being a gate output node, each gate output node having an active load, said active load having a load input;

at least one output sensing circuit having a sensing input, a sensing output, a voltage gain less than unity and a delay, the sensing input being coupled to said at least one gate output, a sensing output coupled to said load input, node coupled to said gate output node, a sensing output coupled to said load input;

said sensing circuit providing negative feedback to said active load, and wherein

an output signal at said a second transistor node swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and an input signal at said first transistor node swings substantially from 1.4 to 1.1.

32. An electrical device comprising:

a logic circuit having at least one logic input node adapted to accept an external signal and forming a device input, at least one logic output node, and at least one logic bias node directly connected to a first current source;

an active load transistor for each said logic output node each active load transistor having a first load node directly connected to a corresponding logic output node, a second load node directly connected to a power rail, and a third load node for receiving a load control signal;

a bias transistor for each load transistor, each bias transistor having a first bias node directly connected to said corresponding logic output node, a second bias node directly connected to said power rail, and a third bias node directly connected both to a second constant current source and to said third load node for supplying said load control signal;

wherein an output signal swing of the logic output node is substantially equal to an input signal swing of the external signal at the logic input node.

33. An electrical device comprising:

a logic circuit having at least one logic input node adapted to accept an external signal and forming a device input, at least one logic output node, and at least one logic bias node connected to a first current source;

an active load transistor for each said logic output node, each active load transistor having a first load node connected to a corresponding logic output node, a second load node connected to a power rail, and a third load node for receiving a load control signal; and

a bias transistor for each load transistor, each bias transistor having a first bias node connected to said corresponding logic output node, a second bias node connected to said power rail, and a third bias node connected both to a second current source and to said third load node for supplying said load control signal, and wherein

an output signal at said at least one logic output node swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and a signal at least one logic input node swings substantially from 1.4 to 1.1.

34. An electrical device as recited in claim 44, wherein said logic circuit is an AND gate.