Embedding a transparency enable bit as part of a resizing bit block transfer operation
First Claim
1. A graphics subsystem for generating pixel values, comprising:
- a host processor generating a display list of parameter values defining a primitive;
a system memory storing said display list of parameter values;
a graphics processor coupled to said host processor and said system memory via a system bus;
wherein said graphics processor includes a resize engine and color compare logic capable of resizing and transparency enabling a source array of pixels in a single operation.
3 Assignments
0 Petitions
Accused Products
Abstract
The present invention includes an integrated resize engine and color compare logic for performing a resize bit block transfer (BitBLT) and a transparency BitBLT in a single operation. A source array of pixels is stretched and/or shrunk based upon control signals. The resized pixel values include red, green, and blue color values which are compared with predetermined color range values stored in register pairs. Preferably a register pair is provided for each color. A set of comparators is provided for each color to compare the register values with the color pixel values and to produce an output signal (IN RANGE) indicating if the color pixel value is within the range established by the register values. Each of the in range signals is provided to multiplex logic which generates a transparency enable (TE) output signal based upon the value of the IN RANGE signals and the value of a SELECT input signal. The transparency (TE) signal is written to a dedicated bit in a pixel value register to embed the transparency enable bit as part of the pixel value. Alternatively, or in addition to the multiplex logic, mask logic may be provided to mask the pixel based upon the IN RANGE output signals.
-
Citations
31 Claims
-
1. A graphics subsystem for generating pixel values, comprising:
-
a host processor generating a display list of parameter values defining a primitive; a system memory storing said display list of parameter values; a graphics processor coupled to said host processor and said system memory via a system bus; wherein said graphics processor includes a resize engine and color compare logic capable of resizing and transparency enabling a source array of pixels in a single operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A graphics subsystem for generating pixel values, comprising:
-
a host processor generating a display list of parameter values defining a primitive; a system memory storing said display list of parameter values; a graphics processor coupled to said host processor and said system memory via a system bus; wherein said graphics processor includes a resize engine and color compare logic capable of resizing and transparency enabling a source array of pixels in a single operation, said resize engine and color compare logic including a resize engine for generating resized color pixel values, and a color compare logic for comparing the resized color pixel values with predetermined threshold values for each of the color pixel values, said resized color pixel values including a red pixel value, a green pixel value, and a blue pixel value, and the color compare logic including; a first pair of registers for defining a range for the color red and a first set of comparators for comparing the range for the color red with the red pixel value; a second pair of registers for defining a range for the color green and a second set of comparators for comparing the range for the color green with the green pixel value; a third pair of registers for defining a range for the color blue and a third set of comparators for comparing the range for the color blue with the blue pixel value; and wherein each of the sets of comparators generates an output signal indicating if the pixel value is within the range defined by the register pairs. - View Dependent Claims (12, 13, 14)
-
-
15. A graphics accelerator capable of providing accelerated graphics operations, comprising:
-
an interface unit for coupling to a system bus; a graphics engine for generating an image; a frame buffer coupled to said graphics engine for storing said image; and a resize engine and color compare logic for resizing the image and embedding a transparency bit enable in the resized image before storing the resized and transparency bit enabled image as a destination array of pixels in the frame buffer. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
-
-
25. A graphics accelerator capable of providing accelerated graphics operations, comprising:
-
an interface unit for coupling to a system bus; a graphics engine for generating an image; a frame buffer coupled to said graphics engine for storing said image; and a resize engine and mask logic for resizing the image and masking portions of the resized image before storing the resized image as a destination array of pixels in the frame buffer. - View Dependent Claims (26, 27, 28)
-
-
29. A method for performing a resize bit block transfer and a transparency bit block transfer as part of a single operation, comprising the steps of:
-
retrieving a source array of pixels from memory; resizing the source array to obtain resized color pixel values; establishing at least one color threshold range; comparing the resized color pixel values with the color threshold range; embedding a transparency enable bit for each resized color pixel value within the color threshold range. - View Dependent Claims (30, 31)
-
Specification