Frame buffer cache for graphics applications

• US 5,909,225 A
• Filed: 05/30/1997
• Issued: 06/01/1999
• Est. Priority Date: 05/30/1997
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Schinnerer, James A., Martin, Robert J.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/866,694
• Time in Patent Office: 732 Days
• Field of Search: 345/507-509, 345/513, 345/518, 345/521, 345/196-198, 345/203, 345/517, 711/118, 711/127-131, 365/189.05, 365/189.08, 365/230.05, 365/230.08
• US Class Current: 345/545
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A frame buffer cache includes a dual-input, dual-output storage cell to multiplex frame buffer tile data and pixel data. Tile data stored in one format while pixel data is stored in a second format. The cache allows for buffering the data in the two different formats so as to provide the data in the format as needed. Pixel data is retrieved from the tile data and file data is retrieved from the pixel data. The storage cell includes a multiple-bit latch and tri-state buffers which connect each storage cell to a tile data bus and a pixel data bus. A number of bus lines and components are reduced due to the use of the tri-state buffers.

Claims

1. A cache for storing data in first and second formats, comprising:

an array of storage elements including one or more tiles, each tile comprised of m rows and n columns of storage elements, each of said m rows of storage elements representing data having a first format, and each of said n columns of storage elements representing data having a second format different that said first format;

a first input bus, coupled to said storage elements of one of said tiles, for writing data in said first format into said n storage elements of a selected row of said tile;

a first output bus, coupled to said storage elements of said one of said tiles, for reading data from said n storage elements of said selected row of said tile to generate said data in said first format;

a second input, bus coupled to said storage elements of said one of said tiles, for writing data in said second format into said m storage elements of a selected column of said tile; and

a second output bus, coupled to said storage elements of said one of said tiles for reading data from said m storage elements of said selected column of said tile to generate data in said second format.

2. The cache as defined in claim 1, wherein said data in said first format is pixel data and said data in said second format is frame buffer data.

3. The cache as defined in claim 1, wherein each of said storage elements comprises:

a latch having inputs and outputs,

an input circuit for connecting said first input bus to the inputs of said latch and for connecting said second input bus to the inputs of said latch, and

an output circuit for connecting the outputs of said latch to said first output bus and for connecting the outputs of said latch to said second output bus.

4. The cache as recited in claim 3, wherein each input circuit comprises:

a first input buffer having an input connected to the first input bus and an output connected to the latch inputs; and

a second input buffer having an input connected to the second input bus and an output connected to the latch inputs.

5. The cache as recited in claim 4, wherein each storage element further comprises:

a first input buffer select line connected to the first input buffer;

a second input buffer select line connected to the second input buffer;

wherein, when the first input buffer select line is asserted, the first input bus is operatively coupled to the latch inputs; and

wherein, when the second input buffer select line is asserted, the second input bus is operatively coupled to the latch inputs.

6. The cache as recited in claim 5, wherein the latch in each storage element is operatively coupled to the first and second input buffer select lines and is enabled when at least one of the first and second input buffer select lines is asserted.

7. The cache as recited in claim 6, wherein each storage element further comprises:

an OR-gate having first and second inputs connected, respectively, to the first and second input buffer select lines and an output connected to an enable input of the latch.

8. The cache as recited in claim 3, wherein each output circuit comprises:

a first output buffer having an input connected to the latch outputs and an output connected to the first output bus; and

a second output buffer having an input connected to the latch outputs and an output connected to the second output bus.

9. The cache as recited in claim 8, wherein the first and second output buffers are each a tri-state device.

10. The cache as recited in claim 8, wherein each storage element further comprises:

a first output buffer select line connected to the first output buffer;

a second output buffer select line connected to the second output buffer;

wherein, when the first output buffer select line is asserted, the latch outputs are operatively coupled to the first output bus; and

wherein, when the second output buffer select line is asserted, the latch outputs are operatively coupled to the second output bus.

11. A dual input, dual output n-bit storage cell having first and second input data buses and first and second output data buses, the storage cell comprising:

a latch having a latch input bus and a latch output bus;

a first input buffer connected between the first input data bus and the latch input bus to operatively couple the first input data bus to the latch input bus;

a second input buffer connected between the second input data bus and the latch input bus to operatively couple the second input data bus to the latch input bus;

a first output buffer connected between the latch output bus and the first output data bus to operatively couple the latch output bus to the first output data bus; and

a second output buffer connected between the latch output bus and the second output data bus to operatively couple the latch output bus to the second output data bus;

an OR-gate having first and second inputs connected, respectively, to the first and second input buffer select lines and an output connected to an enable input of the latch, wherein the latch is enabled when at least one of the first and second input data buses is coupled to the latch.

12. The storage cell as recited in claim 11, wherein the first and second output buffers are each a tri-state buffer.

13. A graphics system for processing and storing data in a first format and a second format, the system comprising:

a memory for storing pixel data in the first format and frame buffer data in said second format, said memory including a bi-directional port;

a cache having storage elements arranged in m rows and n columns, for storing data in said first format in selected rows of said array of storage elements, and for storing data in said second format in selected columns of said array of storage elements; and

a controller for coupling pixel data in said first format to and from said n storage elements of at least one selected row of said storage elements in said cache and for coupling frame buffer data in said second format to and from said m storage elements of at least one selected column of said storage elements from and to said memory through said bi-directional port.

14. The graphics system as recited in claim 13, wherein the memory is a single-port memory.

15. The graphics system as recited in claim 13, wherein the cache further comprises:

a first input bus coupled to said storage elements for coupling data in the first format into a selected row of said storage elements;

a first output bus coupled to said storage elements for coupling data in said first format from said selected row of said storage elements;

a second input bus coupled to said storage elements for coupling data in the second format into a selected column of said storage elements; and

a second output bus coupled to said storage elements for coupling data in said second format from said selected column of said storage elements;

wherein said second input bus and said second output bus are each operatively coupled to the memory.

16. The graphics system as recited in claim 15, wherein each storage element in the array comprises:

a latch having inputs and outputs,

an input circuit for connecting said first input bus to the inputs of said latch and for connecting said second input bus to the inputs of said latch, and

an output circuit for connecting the outputs of said latch to said first output bus and for connecting the outputs of said latch to said second output bus.

17. The system as recited in claim 16, wherein each output circuit comprises:

a first output buffer having an input connected to the latch outputs and an output connected to the first output bus; and

a second output buffer having an input connected to the latch outputs and an output connected to the second output bus.

18. The system as recited in claim 17, wherein in each storage element the first and second output buffers are each a tri-state device.

19. A method of storing and providing data in a first format and a second format different than the first format in an apparatus having a plurality of storage devices connected in an n row and m column configuration, each row of storage devices representing data having the first format, and each column of storage devices representing data having the second format, each storage device having first and second inputs connected, respectively, to first and second input buses and having first and second outputs connected, respectively, to first and second output buses, the method including the steps of:

(a) providing input data in the first format on the first input bus;

(b) storing a respective segment of the input data in a respective storage device in a selected row of the apparatus;

(c) repeating steps (a)-(b) for each row of storage devices; and

(d) outputting to the second output bus the data in each of m storage devices in at least one column to generate data in said second format.

20. The method as recited in claim 19, including steps of:

(e) providing data in the second format on the second input bus;

(f) storing a respective segment of the input data in the second format in a respective m storage devices in a selected column;

(g) repeating steps (e) and (f) for each column of storage devices; and

(h) outputting to the first output bus the data in each of n storage devices in at least one row to generate data in said first format.

21. The method as recited in claim 20, wherein each storage device comprises tri-state buffers connected to the first output bus.

22. The method as recited in claim 21, wherein

the first outputs of the storage devices in each column are connected to one another;

and

the second outputs of the storage devices in each row are connected to one another.

23. A frame buffer assembly comprising:

a single port frame buffer, wherein said single port is utilized to render data to said frame buffer and for reading data for display from said frame buffer; and

a dual port, multiple format frame buffer cache comprising,

frame buffer data input and output ports coupled to said single port frame buffer for transferring data in a frame buffer format;

pixel data input and output ports for transferring data in a pixel data format;

an array of storage elements including one or more tiles, each tile comprised of m rows and n columns of storage elements, each of said n rows of storage elements representing data having a first format, and each of said m columns of storage elements representing data having a second format different that said first format;

a first input bus, coupled to said storage elements of one of said tiles, for writing data in said first format into said n storage elements of a selected row of said tile;

a first output bus, coupled to said storage elements of said one of said tiles, for reading data from said n storage elements of said selected row of said tile to generate said data in said first format;

a second input, bus coupled to said storage elements of said one of said tiles, for writing data in said second format into said m storage elements of a selected column of said tile; and

a second output bus, coupled to said storage elements of said one of said tiles for reading data from said m storage elements of said selected column of said tile to generate data in said second format.