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Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple "jiggles"

  • US 5,909,376 A
  • Filed: 11/20/1995
  • Issued: 06/01/1999
  • Est. Priority Date: 11/20/1995
  • Status: Expired due to Term
First Claim
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1. A process for designing an integrated circuit chip, comprising the steps of:

  • (a) providing a placement of clusters of cells, each cluster being assigned to one of plural predefined and non-overlapping regions on the chip;

    (b) combining the pre-defined and non-overlapping regions to form region groups;

    (c) performing a first cluster placement improvement operation within respective region groups that re-assigns the clusters in each region group to the other pre-defined and non-overlapping regions in said each region group when a cell placement cost function is reduced;

    (d) re-combining the pre-defined and non-overlapping regions to form different region groups; and

    (e) performing a second cluster placement improvement operation within respective different region groups that re-assigns the clusters in each different region group to the other pre-defined and non-overlapping regions in said each different region group when a cell placement cost function is reduced.

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