Refresh sampling built-in self test and repair circuit
First Claim
1. A method for on-chip testing of a memory device that contains a memory array, the method comprising:
- determining failure times for cells in a first subset of the memory array;
calculating one or more statistical parameters based on said failure times;
determining a first refresh pause time based on said one or more statistical parameters; and
applying a data retention test to the memory array using the first refresh pause time, wherein said data retention test identifies an address of a faulty cell within the memory array.
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Accused Products
Abstract
A method for testing a memory device which statistically characterizes the failure time for a subset of cells sampled from the memory array before performing testing of the memory array in general. The memory device includes a testing unit which determines the failure times for cells in the sample subset, and a parameter calculation unit which computes one or more statistical parameters from the failure times. These statistical parameters are then used to determine a refresh pause time which is used in a data retention test of the memory array. The testing method may be performed when power is applied to the memory device. Thus, the BIST method may provide for the accurate detection of memory faults in the memory array at any power-up temperature. In addition, the testing method may be performed after the memory array attains an operational temperature, or in response to an operating system command.
117 Citations
29 Claims
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1. A method for on-chip testing of a memory device that contains a memory array, the method comprising:
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determining failure times for cells in a first subset of the memory array; calculating one or more statistical parameters based on said failure times; determining a first refresh pause time based on said one or more statistical parameters; and applying a data retention test to the memory array using the first refresh pause time, wherein said data retention test identifies an address of a faulty cell within the memory array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system for detecting data retention faults, wherein the system comprises:
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a memory array including a plurality of memory cells; a testing unit coupled to the memory array, and configured to determine the failure times for a first subset of said plurality of memory cells; and a parameter calculation unit coupled to receive said failure times, and configured to determine a first refresh pause time based on said failure times; wherein said testing unit is further coupled to receive the first refresh pause time, and further configured to detect faulty cells among said plurality of memory cells by performing a data retention test using said refresh pause time. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A memory device comprising:
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a plurality of memory cells; a data line; a first weak write circuit coupled to said data line and one or more cells of said plurality of memory cells, wherein said first weak write circuit includes; a first gating device coupled to said data line and said one or more cells; a resistive device coupled to said data line; a second gating device coupled to said resistive device and said one or more cells; and a weak enable line coupled to a first control input of said first gating device and to a second control input of said second gating device; wherein said first gating device is configured to couple said data line to said one or more cells when a first logical value is asserted on said weak enable line; wherein said second gating device is configured to decouple said resistive device from said one or more cells when said first logical value is asserted on said weak enable line; wherein said first gating device is configured to decouple said data line from said one or more cells when a second logical value is asserted on said weak enable line; and wherein said second gating device is configured to couple said resistive device to said one or more cells when said second logical value is asserted on said weak enable line; wherein said second logical value is the complement of said first logical value. - View Dependent Claims (27, 28, 29)
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Specification