System and method for providing scan chain for digital electronic device having multiple clock domains

• US 5,909,451 A
• Filed: 11/21/1996
• Issued: 06/01/1999
• Est. Priority Date: 11/21/1996
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Lach, Jorge E., Ih, Bennet H.
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US08/806,702
• Time in Patent Office: 922 Days
• Field of Search: 371/22.31, 371/22.1, 371/22.36
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence

Abstract

A digital electronic circuit device comprises a plurality of circuit elements, a scan chain establishment element, and a unitary clock domain establishment element. The plurality of circuit elements define a plurality of clock domains, and circuit elements in each clock domain perform processing operations under control of a respective domain clock signal. The scan chain establishment element interconnects the circuit elements in a scan chain to facilitate loading and/or retrieval of a scan vector into and/or out of the digital circuit device. The unitary clock domain establishment element establishes a unitary clock domain for the circuit element when the scan chain establishment element is interconnecting the circuit elements in a scan chain. Thus, the scan vector will be loaded into or retrieved from the digital electronic circuit device using the single, unitary clock signal, thereby avoiding any necessity of using synchronizers or other elements for the scan chain which can complicate layout of the device.

Claims

1. A digital circuit device comprising:

A. a plurality of circuit elements defining a plurality of clock domains, the ones of the circuit elements in each clock domain being adapted to perform operations under control of a respective one of a plurality of domain clock signals, at least one of said domain clock signals having a timing characteristic which differs from that of another of said domain clock signals;

B. a scan chain establishment element adapted to interconnect said circuit elements in an input scan chain to facilitate loading of a scan vector into said plurality of circuit elements; and

C. a unitary clock domain establishment element adapted to establish a unitary clock domain for said circuit elements when said scan chain establishment element is interconnecting said circuit elements in said input scan chain.

2. A digital circuit device as defined in claim 1 in which said unitary clock domain establishment element operates under control of a clock domain control signal to selectively establish said unitary clock domain, the unitary clock domain establishment element enabling said circuit elements to operate under control of a unitary clock signal when said clock domain control signal enables said unitary clock domain establishment element enables said circuit elements to establish said unitary clock domain.

3. A digital circuit element as defined in claim 2 in which said clock domain establishment element enables said circuit elements to operate under control of one of said respective clock domain signals.

4. A digital circuit device as defined in claim 1 in which said circuit elements are enabled to perform a processing operation after said scan vector has been loaded.

5. A digital circuit device as defined in claim 4 in which said unitary clock domain establishment element is further adapted to establish said unitary clock domain when said circuit elements are enabled to perform said processing operation.

6. A digital circuit device as defined in claim 1 in which:

A. said scan chain establishment element is further adapted to interconnect circuit elements in an output scan chain to facilitate retrieval of said scan vector from said digital circuit device; and

B. said unitary clock domain establishment element is further adapted to establish said unitary clock domain for said circuit element when said scan chain establishment element is interconnecting said circuit elements in said output scan chain.

7. A digital circuit device as defined in claim 1 in which at least some of said circuit elements include respective storage devices, said scan chain establishment element including, associated with at least one of said storage devices, a data multiplexer adapted to normally couple digital data from processing circuitry to said at least one of said storage devices, the data multiplexer being responsive to a scan mode signal enabling said scan chain establishment element to establish said scan chain adapted to selectively couple digital data comprising a portion of said scan vector from another of said storage devices to said at least one storage device thereby to enable said portion of said scan vector to be loaded into said at least one of said storage devices.

8. A digital circuit device as defined in claim 7 in which said unitary clock domain establishment element includes, associated with said at least one of said storage devices, a clock multiplexer adapted to normally couple the one of the domain clock signals associated with its circuit element'"'"'s clock domain to clock said at least one of said storage devices, the clock multiplexer being responsive to a clock mode control signal to enable a unitary clock signal to clock said at least one of said storage devices.

9. A digital circuit device as defined in claim 8 in which said storage devices have associated therewith respective clock multiplexers adapted to normally couple the one of the domain clock signals associated with respective ones of their respective circuit element'"'"'s clock domain to clock said respective ones of said of said storage devices, the respective ones of said clock multiplexers being responsive to a unitary clock mode control signal to enable a unitary clock signal to clock said respective ones of said storage devices, thereby to establish said unitary clock domain.

10. A digital circuit device as defined in claim 8 in which:

A. one of said domain clock signals, associated with one of said clock domains, comprises said unitary clock signal, and

B. ones of said storage devices associated with another of said clock domains have associated therewith respective clock multiplexers adapted to normally couple the one of the domain clock signals with said other of said clock domains to their respective circuit element'"'"'s clock domain to clock said respective ones of said of said storage devices, the respective ones of said clock multiplexers being responsive to a unitary clock mode control signal to enable said one of said domain clock signals to clock said respective ones of said storage devices, thereby to establish said unitary clock domain.

11. A digital circuit device as defined in claim 1 in which said timing characteristic is frequency, such that the frequency of the domain clock signal associated with one of said clock domains differs from the frequency of the domain clock signal associated with at least another of said clock domains.

12. A digital circuit device as defined in claim 1 in which said timing characteristic is phase such that the phase of the domain clock signal associated with one of said clock domains differs from the phase of the domain clock signal associated with at least another of said clock domains.

13. A method of operating a digital circuit device comprising a plurality of circuit elements defining a plurality of clock domains, the ones of the circuit elements in each clock domain being adapted to perform operations under control of a respective one of a plurality of domain clock signals, at least one of said domain clock signals having a timing characteristic which differs from that of another of said domain clock signals, the method comprising the steps of:

A. controllably interconnecting said circuit elements in an input scan chain to facilitate loading of a scan vector into said plurality of circuit elements; and

B. controllably establishing a unitary clock domain for said circuit elements when said scan chain establishment element is interconnecting said circuit elements in said input scan chain.

14. A method as defined in claim 13 in which said unitary clock domain establishment step is enabled by a clock domain control signal.

15. A method as defined in claim 14 in which, in the absence of said clock domain control signal, said circuit elements to operate under control of one of said respective clock domain signals.

16. A method as defined in claim 13 further including the step of enabling said circuit elements to perform a processing operation after said scan vector has been loaded.

17. A method as defined in claim 16 in which said unitary clock domain establishment step includes the step of establishing said unitary clock domain when said circuit elements are enabled to perform said processing operation.

18. A method as defined in claim 13 further comprising the steps of:

A. controllably interconnecting circuit elements in an output scan chain to facilitate retrieval of said scan vector from said digital circuit device; and

B. controllably establishing said unitary clock domain for said circuit element when said scan chain establishment element is interconnecting said circuit elements in said output scan chain.

19. A method as defined in claim 13 in which at least some of said circuit elements include respective storage devices, said scan chain establishment step including the steps of:

A. normally coupling digital data from processing circuitry to at least one of said storage devices,

B. responsive to a scan mode signal, establishing said scan chain adapted to selectively couple digital data comprising a portion of said scan vector from another of said storage devices to said at least one storage device thereby to enable said portion of said scan vector to be loaded into said at least one of said storage devices.

20. A method as defined in claim 19 in which said unitary clock domain establishment step includes the steps of, for said at least one of said storage devices,

A. normally coupling the one of the domain clock signals associated with its circuit element'"'"'s clock domain to clock said at least one of said storage devices, and

B. responsive to a clock mode control signal, enabling a unitary clock signal to clock said at least one of said storage devices.

21. A method defined in claim 20 in which, for said storage devices, said unitary clock domain establishment step include the steps of

A. normally coupling the one of the domain clock signals associated with respective ones of respective circuit element'"'"'s clock domain to respective ones of said storage devices to clock said respective ones of said of said storage devices,

B. responsive to a unitary clock mode control signal, enabling said unitary clock signal to clock said respective ones of said storage devices, thereby to establish said unitary clock domain.

22. A method as defined in claim 20 in which:

A. one of said domain clock signals, associated with one of said clock domains, comprises said unitary clock signal,

B. for ones of said storage devices associated with another of said clock domains;

i. the one of the domain clock signals with said other of said clock domains is normally coupled to their respective circuit element'"'"'s clock domain to clock said respective ones of said of said storage devices,

ii. responsive to a unitary clock mode control signal, enabling said one of said domain clock signals to clock said respective ones of said storage devices, thereby to establish said unitary clock domain.

23. A method as defined in claim 13 in which said timing characteristic is frequency, such that the frequency of the domain clock signal associated with one of said clock domains differs from the frequency of the domain clock signal associated with at least another of said clock domains.

24. A method as defined in claim 13 in which said timing characteristic is phase such that the phase of the domain clock signal associated with one of said clock domains differs from the phase of the domain clock signal associated with at least another of said clock domains.

25. A digital circuit device computer program product for enabling a digital data processor to emulate a digital circuit device, said digital circuit device computer program product comprising:

A. a circuit element module adapted to enable said processor to emulate a plurality of circuit elements defining a plurality of clock domains, the ones of the circuit elements in each clock domain performing operations under control of a respective one of a plurality of domain clock signals, at least one of said domain clock signals having a timing characteristic which differs from that of another of said domain clock signals;

B. a scan chain establishment module adapted to enable said processor to emulate interconnection of said circuit elements in an input scan chain to facilitate loading of a scan vector into said plurality of circuit elements; and

C. a unitary clock domain establishment module adapted to enable said processor to emulate establishment of a unitary clock domain for said circuit elements when said scan chain establishment element is interconnecting said circuit elements in said input scan chain.

26. A digital circuit device computer program product as defined in claim 25 in which said unitary clock domain establishment module enables said processor to emulate operation of said circuit element under control of a clock domain control signal to selectively establish said unitary clock domain, the unitary clock domain establishment module enabling said processor to emulate enabling circuit elements to operate under control of a unitary clock signal when said clock domain control signal enables said unitary clock domain establishment element enables said circuit elements to establish said unitary clock domain.

27. A digital circuit element computer program product as defined in claim 26 in which said clock domain establishment module enables said processor to emulate enabling said circuit elements to operate under control of one of said respective clock domain signals.

28. A digital circuit device computer program product as defined in claim 25 further comprising a processing operation control module for enabling said processor to emulate enabling said circuit elements to perform a processing operation after said scan vector has been loaded.

29. A digital circuit device computer program product as defined in claim 28 in which said unitary clock domain establishment module further enables said processor to establish said unitary clock domain when said circuit elements are enabled to perform said processing operation.

30. A digital circuit device computer program product as defined in claim 25 in which:

A. said scan chain establishment module is further adapted to enable said processor to emulate interconnection of said circuit elements in an output scan chain to facilitate retrieval of said scan vector from said digital circuit device; and

B. said unitary clock domain establishment module is further adapted to enable said processor to emulate establishment of said unitary clock domain for said circuit element when said scan chain establishment element is interconnecting said circuit elements in said output scan chain.

31. A digital circuit device computer program product as defined in claim 25 in which circuit element module is adapted to enable said processor emulate at least some of said circuit elements to include respective storage devices, said scan chain establishment module enabling said processor to emulate including, associated with at least one of said storage devices, a data multiplexer adapted to normally couple digital data from processing circuitry to said at least one of said storage devices, the data multiplexer being responsive to a scan mode signal enabling said scan chain establishment element to establish said scan chain adapted to selectively couple digital data comprising a portion of said scan vector from another of said storage devices to said at least one storage device thereby to enable said portion of said scan vector to be loaded into said at least one of said storage devices.

32. A digital circuit device computer program product as defined in claim 31 in which said unitary clock domain establishment module enables said processor to emulate including, associated with said at least one of said storage devices, a clock multiplexer adapted to normally couple the one of the domain clock signals associated with its circuit element'"'"'s clock domain to clock said at least one of said storage devices, the clock multiplexer being responsive to a clock mode control signal to enable a unitary clock signal to clock said at least one of said storage devices.

33. A digital circuit device computer program product as defined in claim 32 in which said circuit element module is adapted to enable said processor to emulate said storage devices having associated therewith respective clock multiplexers adapted to normally couple the one of the domain clock signals associated with respective ones of their respective circuit element'"'"'s clock domain to clock said respective ones of said of said storage devices, the respective ones of said clock multiplexers being responsive to a unitary clock mode control signal to enable a unitary clock signal to clock said respective ones of said storage devices, thereby to establish said unitary clock domain.

34. A digital circuit device computer program product as defined in claim 32 in which said unitary clock domain establishment module enables said processor to emulate:

A. providing one of said domain clock signals, associated with one of said clock domains, as said unitary clock signal, and

B. providing ones of said storage devices associated with another of said clock domains to have associated therewith respective clock multiplexers adapted to normally couple the one of the domain clock signals with said other of said clock domains to their respective circuit element'"'"'s clock domain to clock said respective ones of said of said storage devices, the respective ones of said clock multiplexers being responsive to a unitary clock mode control signal to enable said one of said domain clock signals to clock said respective ones of said storage devices, thereby to establish said unitary clock domain.

35. A digital circuit device computer program product as defined in claim 25 in which said circuit element module, said scan chain establishment module, and said unitary clock domain establishment module comprise code modules encoded on a computer-readable medium.

36. A digital circuit device computer program product as defined in claim 25 in which said timing characteristic is frequency, such that the frequency of the domain clock signal associated with one of said clock domains differs from the frequency of the domain clock signal associated with at least another of said clock domains.

37. A digital circuit device computer program product as defined in claim 25 in which said timing characteristic is phase such that the phase of the domain clock signal associated with one of said clock domains differs from the phase of the domain clock signal associated with at least another of said clock domains.

38. A digital circuit element comprising:

A. a digital storage device including a data input terminal for receiving an input data signal and a clock input terminal for receiving a clock input signal, the digital storage device storing digital data represented by said input data signal in response to successive ticks of the clock input signal;

B. a data multiplexer responsive to a data selection control signal for selectively coupling data from a plurality of diverse data sources as said input data signal to said data input terminal; and

C. a clock multiplexer responsive to a clock selection control signal for selectively coupling clock signals from a plurality of diverse clock signal sources as said clock input signal to said clock input terminal.