System and method for providing scan chain for digital electronic device having multiple clock domains
First Claim
1. A digital circuit device comprising:
- A. a plurality of circuit elements defining a plurality of clock domains, the ones of the circuit elements in each clock domain being adapted to perform operations under control of a respective one of a plurality of domain clock signals, at least one of said domain clock signals having a timing characteristic which differs from that of another of said domain clock signals;
B. a scan chain establishment element adapted to interconnect said circuit elements in an input scan chain to facilitate loading of a scan vector into said plurality of circuit elements; and
C. a unitary clock domain establishment element adapted to establish a unitary clock domain for said circuit elements when said scan chain establishment element is interconnecting said circuit elements in said input scan chain.
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Abstract
A digital electronic circuit device comprises a plurality of circuit elements, a scan chain establishment element, and a unitary clock domain establishment element. The plurality of circuit elements define a plurality of clock domains, and circuit elements in each clock domain perform processing operations under control of a respective domain clock signal. The scan chain establishment element interconnects the circuit elements in a scan chain to facilitate loading and/or retrieval of a scan vector into and/or out of the digital circuit device. The unitary clock domain establishment element establishes a unitary clock domain for the circuit element when the scan chain establishment element is interconnecting the circuit elements in a scan chain. Thus, the scan vector will be loaded into or retrieved from the digital electronic circuit device using the single, unitary clock signal, thereby avoiding any necessity of using synchronizers or other elements for the scan chain which can complicate layout of the device.
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Citations
38 Claims
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1. A digital circuit device comprising:
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A. a plurality of circuit elements defining a plurality of clock domains, the ones of the circuit elements in each clock domain being adapted to perform operations under control of a respective one of a plurality of domain clock signals, at least one of said domain clock signals having a timing characteristic which differs from that of another of said domain clock signals; B. a scan chain establishment element adapted to interconnect said circuit elements in an input scan chain to facilitate loading of a scan vector into said plurality of circuit elements; and C. a unitary clock domain establishment element adapted to establish a unitary clock domain for said circuit elements when said scan chain establishment element is interconnecting said circuit elements in said input scan chain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a digital circuit device comprising a plurality of circuit elements defining a plurality of clock domains, the ones of the circuit elements in each clock domain being adapted to perform operations under control of a respective one of a plurality of domain clock signals, at least one of said domain clock signals having a timing characteristic which differs from that of another of said domain clock signals, the method comprising the steps of:
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A. controllably interconnecting said circuit elements in an input scan chain to facilitate loading of a scan vector into said plurality of circuit elements; and B. controllably establishing a unitary clock domain for said circuit elements when said scan chain establishment element is interconnecting said circuit elements in said input scan chain. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A digital circuit device computer program product for enabling a digital data processor to emulate a digital circuit device, said digital circuit device computer program product comprising:
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A. a circuit element module adapted to enable said processor to emulate a plurality of circuit elements defining a plurality of clock domains, the ones of the circuit elements in each clock domain performing operations under control of a respective one of a plurality of domain clock signals, at least one of said domain clock signals having a timing characteristic which differs from that of another of said domain clock signals; B. a scan chain establishment module adapted to enable said processor to emulate interconnection of said circuit elements in an input scan chain to facilitate loading of a scan vector into said plurality of circuit elements; and C. a unitary clock domain establishment module adapted to enable said processor to emulate establishment of a unitary clock domain for said circuit elements when said scan chain establishment element is interconnecting said circuit elements in said input scan chain. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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38. A digital circuit element comprising:
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A. a digital storage device including a data input terminal for receiving an input data signal and a clock input terminal for receiving a clock input signal, the digital storage device storing digital data represented by said input data signal in response to successive ticks of the clock input signal; B. a data multiplexer responsive to a data selection control signal for selectively coupling data from a plurality of diverse data sources as said input data signal to said data input terminal; and C. a clock multiplexer responsive to a clock selection control signal for selectively coupling clock signals from a plurality of diverse clock signal sources as said clock input signal to said clock input terminal.
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Specification