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Single-chip software configurable transceiver for asymmetric communication system

  • US 5,909,463 A
  • Filed: 11/04/1996
  • Issued: 06/01/1999
  • Est. Priority Date: 11/04/1996
  • Status: Expired due to Term
First Claim
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1. A transceiver for an asymmetric communication system, comprising:

  • a transmit port adapted for coupling to an asymmetrical communication link, said transmit port transmitting data at a first data rate;

    a receive port adapted for coupling to said asymmetrical communication link, said receive port receiving data at a second data rate;

    a signal processor having a data input terminal for receiving a digital transmit signal, a data output terminal for providing a digital receive signal, an input terminal coupled to said receive port, and an output terminal coupled to said transmit port, said signal processor converting said digital transmit signal into a digital representation of an analog transmit signal having a frequency content, and converting a digital representation of an analog receive signal into said digital receive signal according to a frequency content of the digital representation of the analog receive signal;

    said signal processor comprising;

    control means for determining whether said first data rate is a first predetermined data rate and said second data rate is a second predetermined data rate, or whether said first data rate is said second predetermined data rate and said second data rate is said first predetermined data rate; and

    a digital interface having an input coupled to said control means and operable in first and second modes in response to said control means being in a first logic state or a second logic state, respectively, said digital interface converting said digital transmit signal into a plurality of transmit symbols at said first data rate, and converting a plurality of receive symbols received at said second data rate into said digital receive signal,wherein said digital interface uses a first memory buffer for converting said digital transmit signal into said plurality of transmit symbols and uses a second memory buffer which is smaller than said first memory buffer for converting said plurality of receive symbols into said digital receive signal when said control means indicates said first logic state, and wherein said digital interface uses said second memory buffer for converting said digital transmit signal into said plurality of transmit symbols and uses said first memory buffer for converting said plurality of receive symbols into said digital receive signal when said control means indicates said second logic state,wherein said transceiver is selectively operable at either end of said asymmetrical communication link.

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