Method of making memory cell with vertical transistor and buried word and body lines

• US 5,909,618 A
• Filed: 07/08/1997
• Issued: 06/01/1999
• Est. Priority Date: 07/08/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/889,396
• Time in Patent Office: 693 Days
• Field of Search: 438/151, 438/156, 438/242, 438/243, 438/244, 438/268, 438/270
• US Class Current: 438/242
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit. Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in first alternating trenches orthogonal to the bit lines. The buried word lines interconnect ones of the gates. Buried body lines extend in second alternating trenches orthogonal to the bit lines. The buried body lines interconnect body regions of adjacent access transistors. Unitary and split-conductor gate and body lines are provided for shared or independent signals to access transistors on either side of the trenches. In one embodiment, the memory cell has a surface area that is approximately 4 F², where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Claims

1. A method of fabricating an integrated circuit, the method comprising the steps of:

providing a substrate;

forming a plurality of bit lines on the substrate;

forming a plurality of access transistors on each of the bit lines, each access transistor including a first source/drain region shared by at least a portion of the bit line, a body region and second source/drain region formed vertically thereupon;

forming a plurality of isolation trenches in the substrate and orthogonal to the bit lines, each trench located between access transistors on the orthogonal bit lines;

forming in a first one of the trenches a word line that controls conduction between first and second source/drain regions of access transistors that are adjacent to a first side of the first trench; and

forming in a second one of the trenches, adjacent to the first trench, a body line that interconnects body regions of access transistors that are adjacent to a first side of the second trench.

2. The method of claim 1, wherein the word line also controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the first trench.

3. The method of claim 1, wherein the body line also interconnects body regions of access transistors that are adjacent to a second side of the first trench.

4. The method of claim 1, further comprising the step of forming, in the first trench, another word line, which controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the first trench.

5. The method of claim 1, further comprising the step of forming, in the second trench, another body line, which interconnects body regions of access transistors that are adjacent to a second side of the second trench.

6. A method of fabricating an integrated circuit, the method comprising:

forming a first conductivity type first source/drain region layer on a substrate;

forming a second conductivity type body region layer on the first source/drain layer;

forming a first conductivity type second source/drain region layer on the body region layer;

forming a plurality of substantially parallel column isolation trenches extending through the second source/drain region layer, the body region layer, and the first source/drain region layer, thereby forming column bars between the column isolation trenches;

providing an isolation material in the column isolation trenches;

forming a plurality of substantially parallel row isolation trenches, orthogonal to the column isolation trenches, extending through the second source/drain region layer, the body region layer, and at least partially into the first source/drain region layer in the column bars, the row isolation trenches also extending at least partially into the isolation material in the column isolation trenches, thereby forming row bars between the row isolation trenches;

forming an insulating layer at the base of the row isolation trenches;

forming conductive word lines in first alternating ones of the row isolation trenches; and

forming conductive body lines in second alternating ones of the row isolation trenches.

7. The method of claim 6, further comprising the step of forming an insulating layer underlying the column bars.

8. The method of claim 6, further comprising etching median portions of the word lines to provide separate word lines on each side of ones of the row isolation trenches.

9. The method of claim 6, further comprising etching median portions of the body lines to provide separate body lines on each side of ones of the row isolation trenches.