Low capacitance power VFET method and device
First Claim
1. A microelectronic structure comprising:
- a. a n-type layer over a substrate;
b. a p-type carbon doped gate grid structure in said n-type layer which form channels between a source and a drain portion of said n-type layer;
c. a gate contact to said gate structure;
d. a more electrically insulative region of said n-type layer which forms a gate isolation region in said n-type layer below said gate contact to said gate structure;
e. a source contact to said source; and
f. a drain contact to said drain.
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Accused Products
Abstract
A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or deceased thermal dissipation. In a preferred embodiment, the gate capacitance is reduced over prior art methods and structures by etching to the gate 14 and directly contacting the p+ gate with a p-ohmic contact 24. In another embodiment, the area under the gate contact 22 is implanted with a "trim" dopant, where the trim dopant acts to reduce the doping of the drainlayer thereby reducing the capacitance. In another embodiment, the area under the exposed gate contact 22 is isolated by ion damaged to reduce the doping/conductivity of the n- drain layer below a portion of the gate layer to reduce the gate-to-drain capacitance.
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Citations
19 Claims
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1. A microelectronic structure comprising:
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a. a n-type layer over a substrate; b. a p-type carbon doped gate grid structure in said n-type layer which form channels between a source and a drain portion of said n-type layer; c. a gate contact to said gate structure; d. a more electrically insulative region of said n-type layer which forms a gate isolation region in said n-type layer below said gate contact to said gate structure; e. a source contact to said source; and f. a drain contact to said drain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A microelectronic structure comprising:
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a. an n-type first drain/source layer over a substrate; b. a p-type carbon doped gate structure in said n-type first drain/source layer; c. a n-type second drain/source layer over said gate structure; d. a p-ohmic metal gate contact to said gate structure; and e. a more electrically insulative region of said n-type layer which forms a gate isolation region in said first source/drain layer below said p-ohmic metal contact to said gate structure. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification