Wafer fabrication of die-bottom contacts for electronic devices

• US 5,910,687 A
• Filed: 01/24/1997
• Issued: 06/08/1999
• Est. Priority Date: 01/24/1997
• Status: Expired due to Term

• Current Assignee: Chip Systems Innovations, LLC
• Original Assignee: Chipscale
• Inventors: Chen, Changsheng, Marcoux, Phil P., Sander, Wendell B., Young, James L.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/788,762
• Time in Patent Office: 865 Days
• Field of Search: 257/784, 257/773, 257/787, 257/780, 257/501, 257/506
• US Class Current: 257/784
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/13008 Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53242 the principal metal being a noble metal, e.g. gold
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A packaging technique for electronic devices includes wafer fabrication of contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. In one embodiment, a trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold wire extends from a connection point within the circuit into the trench. The gold wire may run over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back thinned to expose the bottom surface of the gold wire. Either the back thinning is selective so as to form a substrate standoff, or an epoxy standoff is applied to the bottom of the substrate. A solderable wire runs onto the standoff from the gold wire exposed on the protrusion, possibly over another insulation layer. If an insulative substrate is used, the insulation layers may be optional. Sawing separates the electronic devices and completes their fabrication, without a subsequent assembly step. In another embodiment, the trench in which the gold wires and the solderable wires connect is formed from the bottom of the substrate after it has been epoxy encapsulated. Optionally, the bottom surface of the substrate of the finished device drops down to be co-planar with the contact bottom surfaces, so as to conduct heat out of the device.

Claims

1. An electronic device having a set of contacts, the device comprising:

a substrate having an electronic circuit having a set of connection points;

an encapsulant having a first portion located above the electronic circuit and the substrate and a second portion extending below the circuit edge forming a protrusion;

an upper set of wires, each having an inner portion located between the substrate and the encapsulant and connecting with one of the connection points, and each having an outer portion extending onto the encapsulant protrusion;

a set of standoffs formed below the bottom surface the substrate; and

a lower set of wires each connecting to one of the upper wires on the encapsulant protrusion where the upper wire is not covered by the substrate, and each lower set of wires extending onto one of the standoffs.

2. The device of claim 1, further comprising:

an upper insulation layer located between the electronic circuit and the upper wires, the upper insulation layer having a through-hole at each connection point and not covering at least a portion of the upper wires on the encapsulant protrusion; and

a lower insulation layer located between the substrate and the lower wires, the lower insulation layer not covering at least a portion of the bottom surface of the upper wires on the encapsulant protrusion.

3. The device of claim 1, wherein a portion of the bottom surface of the substrate is substantially co-planar with the lower wires.

4. The device of claim 1, wherein the substrate is formed of material selected from the group consisting essentially of silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire, and quartz.

5. The device of claim 1, wherein the electronic circuit is selected from the group consisting of an integrated circuit fabricated using the substrate, an electronic circuit fabricated using the substrate, an active discrete electronic component fabricated using the substrate, a passive discrete electronic component fabricated using the substrate, an integrated circuit attached to the substrate, an electronic circuit attached to the substrate, an active discrete electronic component attached to the substrate, and a passive discrete electronic component attached to the substrate.

6. The device of claim 1, wherein the upper wires are formed of material selected from the group consisting essentially of gold, silver, copper, aluminum, nickel, and layers thereof.

7. The device of claim 1, wherein the encapsulant is formed of material selected from the group consisting essentially of epoxy, plastic, glass, polymide resin, Teflon, silicon oxide, silicon nitride, silicon, polysilicon, amorphous silicon, aluminum, diamond, and layers thereof.

8. The device of claim 1, wherein the lower wires are formed of material selected from the group consisting essentially of gold, silver, nickel, nichrome-gold, nichrome-nickel, nickel-arsenic-gold, nickel-arsenic, nickel-gold, gold-tin-oxide, palladium-silicide, titanium, tungsten, titanium-tungsten, indium titanium oxide, aluminum, copper, platinum, alloys thereof, and layers thereof.

9. The device of claim 2, wherein the upper insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, patternable plastics, mixtures thereof, and layers thereof.

10. The device of claim 2, wherein the lower insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, pattemable plastics, mixtures thereof, and layers thereof.

11. An electronic device having a set of contacts, the device comprising:

substrate means for holding an electronic circuit that includes a set of connection points;

encapsulant means that is located above the electronic circuit and the substrate and that forms a protrusion below the circuit edge;

upper wire means for connecting connection points to another set of points on the encapsulant protrusion;

standoff means, formed below the bottom surface of the substrate; and

lower wire means for connecting to the points on the upper wire means and for extending onto the substrate post means.

12. An electronic device having a set of contacts, the device comprising:

a substrate having an electronic circuit that includes a set of connection points;

an encapsulant having one portion located above the electronic circuit and the substrate and another portion extending below the circuit edge and there forming a protrusion;

an upper set of wires, each having an inner portion located between the substrate and the encapsulant and connecting with one of the connection points, and each having an outer portion extending onto the encapsulant protrusion;

a set of standoffs formed from the substrate; and

a lower set of wires, each connecting to one of the upper wires on the encapsulant protrusion where the upper wire is not covered by the substrate, and each extending onto one of the substrate standoffs.

13. The device of claim 12, further comprising:

an upper insulation layer located between the electronic circuit and the upper wires, the upper insulation layer having a through-hole at each connection point and not covering at least a portion of the upper wires on the encapsulant protrusion; and

a lower insulation layer located between the substrate and the lower wires, the lower insulation layer not covering at least a portion of the bottom surface of the upper wire on the encapsulant protrusion.

14. The device of claim 12, wherein a portion of the bottom surface of the substrate is substantially co-planar with the lower set of wires.

15. The device of claim 12, wherein the substrate is formed of material selected from the group consisting essentially of silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire, and quartz.

16. The device of claim 12, wherein the electronic circuit is selected from the group consisting of an integrated circuit fabricated using the substrate, an electronic circuit fabricated using the substrate, an active discrete electronic component fabricated using the substrate, a passive discrete electronic component fabricated using the substrate, an integrated circuit attached to the substrate, an electronic circuit attached to the substrate, an active discrete electronic component attached to the substrate, and a passive discrete electronic component attached to the substrate.

17. The device of claim 12, wherein the upper wires are formed of material selected from the group consisting essentially of gold, silver, copper, aluminum, nickel, and layers thereof.

18. The device of claim 12, wherein the encapsulant is formed of material selected from the group consisting essentially of epoxy, plastic, glass, polymide resin, Teflon, silicon oxide, silicon nitride, silicon, polysilicon, amorphous silicon, aluminum, diamond, and layers thereof.

19. The device of claim 12, wherein the lower wires are formed of material selected from the group consisting essentially of gold, silver, nickel, nichrome-gold, nichrome-nickel, nickel-arsenic-gold, nickel-arsenic, nickel-gold, gold-tin-oxide, palladium-silicide, titanium, tungsten, titanium-tungsten, indium titanium oxide, aluminum, copper, platinum, alloys thereof, and layers thereof.

20. The device of claim 13, wherein the upper insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, pattemable plastics, mixtures thereof, and layers thereof.

21. The device of claim 13, wherein the lower insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, pattemable plastics, mixtures thereof, and layers thereof.

22. An electronic device having a set of contacts, the device comprising:

a substrate means for holding an electronic circuit that includes a set of connection points;

an encapsulant means that is located above the electronic circuit and the substrate and that forms a protrusion below the circuit edge;

an upper set of wire means for connecting the connection points to another set of points on the encapsulant protrusion;

a set of standoff means, formed from the substrate; and

a lower set of wire means for connecting to the points on the upper wire means and for extending onto the set of standoff means.

23. An electronic device having a set of contacts, the device comprising:

a substrate having an electronic circuit that includes a set of connection points;

an encapsulant located above the electronic circuit and the substrate;

an upper set of wires, each having an inner portion located between the substrate and the encapsulant and connecting with one of the connection points, and each having an outer portion extending beyond the edge of the electronic circuit;

a set of standoffs formed from the substrate; and

a lower set of wires, each connecting to one of the upper wires at a point within its outer portion, and each extending onto one of the substrate standoffs.

24. The device of claim 23, further comprising:

an upper insulation layer located between the electronic circuit and the upper wires, the upper insulation layer having a through-hole at each connection point and not covering at least part of the outer portion of the upper wires; and

a lower insulation layer located between the substrate and the lower wires, the lower insulation layer not covering at least part of the outer portion of the upper wires.

25. The device of claim 23, wherein a portion of the bottom surface of the substrate is substantially co-planar with the lower set of wires.

26. The device of claim 23, wherein the substrate is formed of material selected from the group consisting essentially of silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire, and quartz.

27. The device of claim 23, wherein the electronic circuit is selected from the group consisting of an integrated circuit fabricated using the substrate, an electronic circuit fabricated using the substrate, an active discrete electronic component fabricated using the substrate, a passive discrete electronic component fabricated using the substrate, an integrated circuit attached to the substrate, an electronic circuit attached to the substrate, an active discrete electronic component attached to the substrate, and a passive discrete electronic component attached to the substrate.

28. The device of claim 23, wherein the upper wires are formed of material selected from the group consisting essentially of gold, silver, copper, aluminum, nickel, and layers thereof.

29. The device of claim 23, wherein the encapsulant is formed of material selected from the group consisting essentially of epoxy, plastic, glass, polymide resin, Teflon, silicon oxide, silicon nitride, silicon, polysilicon, amorphous silicon, aluminum, diamond, and layers thereof.

30. The device of claim 23, wherein the lower wires are formed of material selected from the group consisting essentially of gold, silver, nickel, nichrome-gold, nichrome-nickel, nickel-arsenic-gold, nickel-arsenic, nickel-gold, gold-tin-oxide, palladium-silicide, titanium, tungsten, titanium-tungsten, indium titanium oxide, aluminum, copper, platinum, alloys thereof, and layers thereof.

31. The device of claim 24, wherein the upper insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, patternable plastics, mixtures thereof, and layers thereof.

32. The device of claim 24, wherein the lower insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, pattemable plastics, mixtures thereof, and layers thereof.

33. An electronic device having a set of contacts, the device comprising:

a substrate means for holding an electronic circuit that includes a set of connection points;

an encapsulant means that is located above the electronic circuit and the substrate;

an upper set of wire means for connecting the connection points to another set of points beyond the edge of the electronic circuit;

a set of standoff means formed from the substrate; and

a lower set of wire means for connecting to the points on the upper wire means and for extending onto the standoff means.

34. An electronic device having a set of contacts, the device comprising:

a substrate having an electronic circuit that includes a set of connection points;

an encapsulant located above the electronic circuit and the substrate;

an upper set of wires, each having an inner portion located between the substrate and the encapsulant and connecting with one of the connection points, and each having an outer portion extending beyond the edge of the electronic circuit;

a set of standoffs formed below the bottom surface the substrate; and

a lower set of wires, each connecting to one of the upper wires at a point within its outer portion, and each extending onto one of the standoffs.

35. The device of claim 34, further comprising:

an upper insulation layer located between the electronic circuit and the upper wires, the upper insulation layer having a through-hole at each connection point and not covering at least part of the outer portion of the upper wires; and

a lower insulation layer located between the substrate and the lower wires, the lower insulation layer not covering at least part of the outer portion of the upper wires.

36. The device of claim 34, wherein a portion of the bottom surface of the substrate is substantially co-planar with the lower wires.

37. The device of claim 34, wherein the substrate is formed of material selected from the group consisting essentially of silicon, gallium arsenide, silicon germanium, silicon carbide, gallium phosphide, ceramic materials, sapphire, and quartz.

38. The device of claim 34, wherein the electronic circuit is selected from the group consisting of an integrated circuit fabricated using the substrate, an electronic circuit fabricated using the substrate, an active discrete electronic component fabricated using the substrate, a passive discrete electronic component fabricated using the substrate, an integrated circuit attached to the substrate, an electronic circuit attached to the substrate, an active discrete electronic component attached to the substrate, and a passive discrete electronic component attached to the substrate.

39. The device of claim 34, wherein the upper wires are formed of material selected from the group consisting essentially of gold, silver, copper, aluminum, nickel, and layers thereof.

40. The device of claim 34, wherein the encapsulant is formed of material selected from the group consisting essentially of epoxy, plastic, glass, polymide resin, Teflon, silicon oxide, silicon nitride, silicon, polysilicon, amorphous silicon, aluminum, diamond, and layers thereof.

41. The device of claim 34, wherein the lower wires are formed of material selected from the group consisting essentially of gold, silver, nickel, nichrome-gold, nichrome-nickel, nickel-arsenic-gold, nickel-arsenic, nickel-gold, gold-tin-oxide, palladium-silicide, titanium, tungsten, titanium-tungsten, indium titanium oxide, aluminum, copper, platinum, alloys thereof, and layers thereof.

42. The device of claim 34, wherein the upper insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, pattemable plastics, mixtures thereof, and layers thereof.

43. The device of claim 35, wherein the lower insulation layer is formed of material selected from the group consisting essentially of silicon oxide, silicon nitride, aluminum oxide, polymide resins, epoxy, acrylics, pattemable plastics, mixtures thereof, and layers thereof.

44. An electronic device having a set of contacts, the device comprising:

a substrate means for holding an electronic circuit that includes a set of connection points;

an encapsulant means located above the electronic circuit and the substrate;

an upper set of wire means for connecting the connection points to another set of points on the encapsulant protrusion;

a set of standoff means, formed below the bottom surface of the substrate; and

a lower set of wire means for connecting to the points on the upper wire means and for extending onto the standoff means.