Power amplifier in bicmos technology having an output stage in MOS technology

• US 5,910,748 A
• Filed: 07/16/1997
• Issued: 06/08/1999
• Est. Priority Date: 07/16/1996
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Chaussy, Danika, Reffay, Marius
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US08/893,248
• Time in Patent Office: 692 Days
• Field of Search: 326/83, 326/84, 323/315, 327/103, 327/108, 327/432, 327/433, 327/560
• US Class Current: 327/432
• CPC Class Codes: H03F 3/3001 with field-effect transistors
• CPC Class Codes: H03F 3/345 with field-effect devices H03F3/347 takes precedence

Abstract

The present invention relates to a power amplifier having an output stage in MOS technology, including an upper half-output stage comprised of two P-channel MOS power transistors mounted as a current mirror, a lower half-output stage comprised of two N-channel MOS power transistors mounted as a current mirror, an output terminal of the amplifier corresponding to the common drains of a first MOS transistor of the upper stage and of a first MOS transistor of the lower stage, and a control stage in bipolar technology for setting, according to a control voltage, two control currents of the half-output stages.

Claims

1. A power amplifier having an output stage in MOS technology, including:

an upper half-output stage comprised of a first and a second P-channel MOS power transistors mounted as a current mirror;

a lower half-output stage comprised of a first and a second N-channel MOS power transistors mounted as a current mirror;

an output terminal corresponding to the common drains of the first P-channel MOS power transistor of the upper half-output stage and of the first N-channel MOS power transistor of the lower half-output stage; and

a control stage in bipolar technology for setting, according to a control voltage, two control currents of the upper half-output stage and the lower half-output stage, the control stage including;

a first PNP-type bipolar transistor setting a first current for controlling the upper half-stage;

a second NPN-type bipolar transistor setting a second current for controlling the lower half-stage; and

an input terminal for receiving the control voltage and connected to the respective bases of the first and second bipolar transistors.

2. The amplifier according to claim 1 wherein the control stage further includes:

a third NPN-type bipolar transistor interposed between the first bipolar transistor and a current control terminal of the upper half-stage;

a first source of a reference current, an output terminal of which is connected to the collector of a fourth NPN-type bipolar transistor, mounted in a current mirror with the third transistor and connected, via a fifth bipolar transistor, to a negative line; and

a sixth NPN-type bipolar transistor, diode-mounted between an output terminal of a second source of a reference current and the negative line, the base of the sixth transistor being connected to the base of the fifth transistor.

3. The amplifier according to claim 2 wherein a seventh NPN-type bipolar transistor is interposed between a positive line and the common bases of the third and fourth transistors, the base of the seventh transistor being connected to the collector of the fourth transistor.

4. The amplifier according to claim 2 wherein resistors of same value are interposed between the respective emitters of the second and sixth bipolar transistors and the negative line, resistors of same value being interposed, respectively, between the first and third bipolar transistors and between the fourth and fifth transistors.

5. The amplifier according to claim 2 wherein the reference currents of first and second sources of reference current are identical.

6. The amplifier according claim 1 including an additional current mirror, such that the collector of the second bipolar transistor is connected to the drain of a third MOS transistor in the additional current mirror and the collector current of the second bipolar transistor copied onto the drain of the second N-channel MOS power transistor.

7. The amplifier according to claim 6 wherein the third MOS transistor of the additional current mirror is comprised of two P-channel MOS transistors.

8. The amplifier according to claim 1 wherein the current mirrors constitutive of the upper and lower half-stages exhibit a same ratio.

9. A power amplifier implemented in bipolar and MOS technology comprising:

a first output stage having a first and second MOS transistor connected as a current mirror;

a second output stage having a first and second MOS transistor connected as a current mirror;

an output terminal coupled to the output stages; and

a control stage having bipolar transistors, the control stage having an input terminal for receiving a control voltage and providing, based on the control voltage, a control current through each of the respective output stages, wherein the current through each of the respective output stages is equal when the control voltage is zero.

10. The power amplifier of claim 9 wherein the control stage further comprises:

a first bipolar transistor of a first type providing the control current for the upper-half output stage;

a second bipolar transistor of a second type providing the control current for the lower-half output stage; and

an input terminal for receiving the control voltage coupled to the bases of both of the bipolar transistors.

11. The power amplifier of claim 9 wherein the control stage further comprises:

a third bipolar transistor having the second type connected in a mirror configuration to a fourth bipolar transistor having the second type, the third bipolar transistor adapted to control the current of the upper half output stage;

a first current source connected to a negative line through the fourth bipolar transistor and a fifth bipolar transistor having the first type; and

a sixth bipolar transistor having the second type connected in a mirror configuration to the fifth bipolar transistor, the sixth bipolar transistor connected between a second current source and the negative line.

12. The power amplifier of claim 11 wherein the control stage further comprises:

a seventh bipolar transistor having the second type connected between a positive line and common bases of the third and fourth transistors, the base of the seventh bipolar transistor coupled to the first current source.

13. The power amplifier of claim 11 wherein the control stage further comprises:

two resistors of a first value, one each connected between the emitters of the second and sixth bipolar transistors and the negative line;

one resistor having a second value connected between the fourth and fifth bipolar transistors; and

one resistor having the second value connected between the first and fourth bipolar transistors.

14. The power amplifier of claim 11 wherein current from the first current source and the second current source have the same values.

15. The power amplifier of claim 9 wherein the control stage further includes:

a third MOS current mirror duplicating the control current set by the control voltage and providing the duplicated control current to the drain of the second MOS transistor of the lower-half output stage.

16. The power amplifier of claim 9 wherein the current mirror of the upper-half output stage and the current mirror of the lower-half output stage have the same ratio.

17. The power amplifier of claim 9 wherein the first and second MOS transistors connected as a current mirror in the second output stage have N-type channels.

18. The power amplifier of claim 10 wherein the bipolar transistor of the first type is a PNP transistor.