Frequency demodulator with resampled output

• US 5,910,752 A
• Filed: 12/09/1997
• Issued: 06/08/1999
• Est. Priority Date: 12/09/1997
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Filipovic, Daniel, Younis, Saed G.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/987,307
• Time in Patent Office: 546 Days
• Field of Search: 329/341-343, 455/205, 455/214, 455/337, 375/324, 375/328, 375/334-337
• US Class Current: 329/341
• CPC Class Codes: H03D 2200/005 Analog to digital conversion
• CPC Class Codes: H03D 2200/0056 including a digital decimation filter
• CPC Class Codes: H03D 2200/0062 Computation of input samples, e.g. successive samples
• CPC Class Codes: H03D 2200/0064 Detection of passages through null of a signal
• CPC Class Codes: H03D 3/006 by sampling the oscillations and further processing the samples, e.g. by computing techniques H03D3/007 takes precedence

Abstract

An receiver receives, amplifies, filters, and downconverts an RF signal to obtain an FM signal. The FM signal is then limited by a limiter and sampled by an ADC. The FM samples from the ADC are provided to an edge detector which detects transitions in the FM samples. The transitions correspond to zero crossings in the FM signal. The time period between the zero crossings, or the cycle width, is measured with a counter to determine the instantaneous frequency f_c of the FM signal. The demodulated output is proportional to the instantaneous frequency which can be determined from the measured cycle periods as f_c =1/2T_c, f_c ≈-αT_c, or f_c ∝T_c, where T_c is the measured cycle period, and α is a constant based on the slope of 1/2T_c,avg, where T_c,avg is the average cycle period. The sample rate of the demodulated output can be reduced, through resampling, to minimize power consumption in the subsequent signal processing blocks.

Claims

1. An FM demodulator comprising:

an analog-to-digital converter (ADC) for receiving an FM signal and producing FM samples;

a demodulator processor connected to said ADC for receiving said FM samples and producing FM output, said demodulator processor including;

edge detector, said edge detector receiving said FM samples and producing pulses;

counter, connected to said edge detector, said counter producing a measured cycle period based on said pulses from said edge detector;

first register connected to said counter, said first register producing a demodulated output based on said measured cycle period from said counter;

second register connected to said first register, said second register producing a resampled output based on said demodulated output from said first register.

2. The receiver of claim 1 further comprising:

a limiter connected to said ADC, said limiter receiving said FM signal and producing a limited FM signal; and

wherein said ADC receives said limited FM signal and produces FM samples.

3. The receiver of claim 1 wherein said ADC is a 1-bit converter.

4. A method for demodulating an FM signal comprising the steps of:

sampling said FM signals with an analog-to-digital converter (ADC) to produce FM samples;

detecting transmissions in said FM samples;

measuring cycle periods based on said detection of transition in said FM samples;

latching said measured cycle periods to produce a demodulated output;

resampling said demodulated output to produce a resampled output;

calculating an FM output based on said measured cycle periods based on said demodulated output and said resampled output.

5. The method of claim 4 wherein said calculating step comprises the step of:

computing an instantaneous frequency f_c in accordance with a relationship f_c =1/2T_c, where T_c is a width of said measured cycle periods; and

wherein said calculating step is based on said computed instantaneous frequency.

6. The method of claim 4 wherein said calculating step comprises the step of:

computing an instantaneous frequency f_c in accordance with a relationship f_c ≈

-α

T_c, where T_c is the measured cycle period, α

is a constant based on a slope of f_c =1/2T_c,avg, where T_c,avg is an average width of said measured cycle periods; and

wherein said calculating step is based on said computed instantaneous frequency.

7. The method of claim 4 wherein said calculating step comprises the step of:

computing an instantaneous frequency f_c in accordance with a relationship f_c ∝

T_c, where T_c is a width of said measured cycle period; and

wherein said calculating step is based on said computed instantaneous frequency.

8. The method of claim 4 further comprising the step of:

filtering said demodulated output to produce a filtered output; and

wherein said calculating step is based on said filtered output.

9. The method of claim 4 wherein said FM samples are 1-bit samples.

10. The method of claim 9 wherein said FM signal comprises a modulated carrier sinusoid having a carrier frequency of 80 KHz.

11. The method of claim 10 wherein said ADC is clocked with a 19.68 MHz sampling clock.

12. The method of claim 11 wherein said resampling step is performed with a resampling clock having a frequency which is 1/41 of said sampling clock.