Circuit design methods and tools

• US 5,910,898 A
• Filed: 12/14/1995
• Issued: 06/08/1999
• Est. Priority Date: 12/14/1995
• Status: Expired due to Term

• Current Assignee: Viewlogic Systems, Inc. (Siemens AG)
• Original Assignee: Viewlogic Systems, Inc. (Siemens AG)
• Inventors: Johannsen, David L.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US08/572,520
• Time in Patent Office: 1,272 Days
• Field of Search: 364/488, 364/489, 364/490, 364/578, 364/757, 364/491, 326/39
• US Class Current: 716/103
• CPC Class Codes: G06F 2207/3852 Calculation with most significant digit first
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 7/5318 with column wise addition of partial products, e.g. using Wallace tree, Dadda counters G06F7/5324 takes precedence

Abstract

A circuit design tool which includes (1) separating structural and functional aspects of components, so as to specify the desired functional behaviour of the component, leaving the actual gate-level design of the component to the design tool; (2) translating a model of the desired logical behaviour of a circuit into a regularized set of functional components to achieve that desired behaviour; (3) verifying structural equivalence between pairs of components; (4) a method for bit-reversing the signal flow in a component; (5) a method for performing arithmetic operations backwards from a natural order; (6) an architecture for a multiplier which is faster and more compact than known multipliers; and (7) a method of translating a logic equation into a netlist of connected logic gates.

Claims

1. A method for bit-reversing signal flow in the operation of a circuit design tool, said method comprising the steps of:

receiving a first description of a component structure having a set of bitslices, each one of said set of bitslices having a logic block, and each one of said set of bitslices operating on an input bit, producing an output bit, having a carry signal input and a carry signal output, wherein a carry signal output corresponding to a selected one of said set of bitslices is coupled to a carry signal input of a next one of said set of bitslices, said carry signal output being responsive to said carry signal input, said carry signals having a directional signal flow;

replacing each one of said set of bitslices with a first carry-logic block and a second logic block representing behavioral characteristics of said one of said set of bitslices;

replacing carry-logic blocks coupled in series with a merge-carry block;

constructing a logical truth table in response to said replacing steps;

combining said second logic block with said merge-carry block using said logical truth table; and

constructing a functional description for each said second logic block.

2. A method according to claim 1, wherein said carry signal output is low independent of said carry signal input.

3. A method according to claim 1, wherein said carry signal output is high independent of said carry signal input.

4. A method according to claim 1, wherein said carry signal output is the same as said carry signal input.

5. A method according to claim 1, wherein said carry signal output is the inverse of said carry signal input.

6. A method according to claim 1, wherein said component comprises an arithmetic function.

7. The method according to claim 1, wherein said step of replacing each one of said set of bitslices further includes the following sub-steps:

obtaining a truth table for each logic block corresponding to each one of said set of bitslices;

decomposing said truth table;

assigning an encoding to said truth table; and

generating a truth table in response to said step of assigning.

8. The method according to claim 7, wherein said step of assigning further includes the following sub-steps:

assigning an encoding for said output bit of each one of said set of bitslices when in a first state; and

assigning an encoding for said carry signal output of each one of said set of bitslices when in a second state.

9. The method according to claim 1, wherein said step of constructing a logical truth table further includes the following sub-steps:

constructing a circuit having a first copy and a second copy of each said logic block;

coupling said first copy to a first carry input value, producing a first output;

coupling said second copy to a second carry input value, producing a second output;

coupling said first output and said second output to a remapping block, producing a set of outputs; and

constructing a set of logic equations corresponding to said set of outputs.

10. A method for verifying structural equivalence of a first circuit structure and a second circuit structure in the operation of a circuit design tool, said method comprising the steps of:

receiving a description of the first circuit structure and a description of the second circuit structure;

verifying that for each port/pin in said first description there is an equivalent port/pin in said second description;

verifying that for each port/pin in said second description there is an equivalent port/pin in said first description;

removing each delay gate and each time gate from said first structural description;

removing each delay gate and each time gate from said second structural description;

wherein each said delay gate includes an input and an output, said delay gate passing said input through to said output after a delay of one clock cycle, and

wherein each said time gate includes an input, an output, and a designated clock cycle, wherein said in put is passed through to said output in said designated clock cycle;

applying a set of replacement rules to said first structural description and said second structural description; and

verifying equivalence of said first and second structural descriptions resulting from said applying step.

15. A method according to claim 10, said step of verifying equivalence comprising the sub-steps of:

matching input bits of said first structural description to input bits of said second structural description;

matching output bits of said first structural description to output bits of said second structural description;

matching logic connections coupled to said output bits of said first structural description to logic connections coupled to said output bits of said second structural description; and

matching logic blocks coupled to said logic connections of said first structural description to logic blocks coupled to said logic connections of said second structural description.

11. A method according to claim 19, both of said removing steps further comprising the sub-steps of:

determining a number T of used clock cycles;

constructing T copies of said structural description;

coupling input and output bits for each one of said T clock cycles to corresponding copies of said structural description;

replacing each time gate within each one of said T copies of said structural description with a connection from its clock cycle t to a next clock cycle t+1; and

removing each unused logic block from each one of said T copies of said structural description, wherein each logic block comprises a set of input values, a set of output values, and is associated with a logic equation used to generate said set of output values from said set of input values.

12. A method according to claim 11, wherein a clock cycle is used if a time gate is active during said clock cycle, or if a bit appears at an input node during said clock cycle, or a bit is valid at an output node during said clock cycle.

13. A method according to claim 11, wherein a logic block is used if said logic block is coupled to at least one other logic block.

14. A method according to claim 11, wherein a logic block is used if said logic block'"'"'s outputs are propagated to an output bit.