Method for performing floorplan timing analysis using multi-dimensional feedback in a spreadsheet with computed hyperlinks to physical layout graphics and integrated circuit made using same

• US 5,910,899 A
• Filed: 10/25/1996
• Issued: 06/08/1999
• Est. Priority Date: 10/25/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Barrientos, Carlo E.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/736,920
• Time in Patent Office: 956 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578
• US Class Current: 716/118
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A computer-implemented method for aiding in the design of an integrated circuit (IC) floorplan. The method comprises receiving a netlist, physical layout information, and timing constraints of the IC and performing timing analysis of the signal paths of the IC. The user selects the set of nets to by analyzed. The timing analysis comprises calculating net delays as a function of the length of the signal paths. The timing analysis further comprises calculating slack times by subtracting from the clock cycle time of the IC the sum of the driven at timing constraint, the needed by timing constraint, and the net delay. Paths which have a slack time greater than a slack failure value are passing nets and paths which have a slack time greater than a slack failure value are failing nets. The slack failure value is user-specifiable and defaults to zero. The method further comprises displaying in a spreadsheet the timing constraints, net delays, and slack times for each path selected, thus providing the designer with complex multi-dimensional feedback. The feedback for each path in the spreadsheet is accompanied by a hyperlink button, which the designer selects in order to graphically display the path on a graphical view of the floorplan. Thus the designer is enabled to relate the non-graphical timing information to a graphical display of the paths and apply his or her intuitive knowledge to make necessary changes to the floorplan. The timing information is further summarily displayed in a histogram, thus providing visual feedback regarding the timing quality of the floorplan. The method provides means for the designer to display failing paths, passing paths, all paths, and paths skipped in timing analysis due to the absence of timing constraints.

Claims

1. A computer-implemented method for aiding in the design of an integrated circuit floorplan, wherein said method is performed on a computer system comprising a display screen, an input device, and a processor, the method comprising:

receiving a floorplan comprising elements of an integrated circuit arranged across a layout space, said floorplan includes a plurality of nets which extend between a plurality of terminals arranged at specified coordinates within said physical layout space;

receiving timing constraints for at least a pair of said plurality of terminals;

calculating a net delay for a signal path, wherein said signal path comprises a portion of one of said plurality of nets, said portion extending between the pair of said plurality of terminals;

calculating a slack time as a function of said net delay and said timing constraints;

displaying on the display screen said slack time in a spreadsheet format; and

creating at least one hyperlink between information within said floorplan and information within said spreadsheet.

2. The method as recited in claim 1, further comprising:

displaying on the display screen in said spreadsheet said timing constraints.

3. The method as recited in claim 1, wherein said hyperlink is associated with said signal path such that said hyperlink is configured for selecting said signal path and is selected in response to user input upon said input device.

4. The method as recited in claim 3, wherein said user input upon the input device corresponds to selection of said hyperlink.

5. The method as recited in claim 3, further comprising:

displaying said floorplan on said display screen; and

displaying said signal path on the floorplan on the display screen in response to said selecting.

6. The method as recited in claim 1, wherein said hyperlink is associated with one of said plurality of nets such that said hyperlink is configured for selecting said one of said plurality of nets and is selected in response to user input upon said input device.

7. The method as recited in claim 6, further comprising:

displaying on the display screen the integrated circuit floorplan;

displaying said one of said plurality of nets on the floorplan on the display screen in response to said selecting.

8. The method as recited in claim 1, wherein each of said plurality of nets comprises at least one source terminal and at least one destination terminal, wherein said timing constraints comprise a driven at timing constraint associated with each of said at least one source terminal and a needed by timing constraint associated with each of said at least one destination terminal, wherein said pair of said plurality of terminals of said signal path comprises a source terminal and a destination terminal.

9. The method as recited in claim 8, wherein said calculating said net delay comprises:

calculating a rectilinear length between said source terminal and said destination terminal and multiplying said length by a predetermined delay per unit length time.

10. The method as recited in claim 8, wherein said integrated circuit is designed to operate at a predetermined clock cycle time.

11. The method as recited in claim 10, wherein said calculating said slack time comprises subtracting from said clock cycle time a sum of said driven at timing constraint, said needed by timing constraint, and said net delay for said signal path.

12. The method as recited in claim 11, further comprising:

determining if the slack time for said signal path is less than a slack failure value.

13. The method as recited in claim 12, further comprising:

displaying on the display screen in said spreadsheet a visual indicator for indicating if the slack time is less than the slack failure value.

14. The method as recited in claim 12, wherein said slack failure value is specified by user input.

15. The method as recited in claim 12, wherein said slack failure value is zero.

16. The method as recited in claim 12, further comprising:

setting said net delay to a zero value;

calculating said slack time to determine instances in which said floorplan fails to satisfy said timing constraints.

17. The method as recited in claim 1, further comprising:

selecting at least one signal path of said integrated circuit in response to user input;

wherein said calculating a slack time comprises calculating slack times for said at least one signal path selected.

18. The method as recited in claim 1, further comprising:

selecting at least one net of said integrated circuit in response to user input;

wherein said calculating a slack time comprises calculating slack times for each signal path associated with said at least one net selected.

19. The method as recited in claim 1, further comprising:

displaying on the display screen in said spreadsheet source and destination terminal identifiers associated with said signal path.

20. The method as recited in claim 1, further comprising:

displaying on the display screen in said spreadsheet said net delay.

21. A computer-readable storage media for operating in a computer system, the computer system including a display screen, an input device, memory, and a processor, wherein the storage media includes a substrate having a physical configuration representing data, the storage media comprising:

instructions for receiving a floorplan comprising elements of an integrated circuit arranged across a layout space, said floorplan includes a plurality of nets which extend between a plurality of terminals arranged at specified coordinates within said physical layout space;

instructions for receiving timing constraints for at least a pair of said plurality of terminals;

instructions for calculating a net delay for a signal path, wherein said signal path comprises a portion of one of said plurality of nets, said portion extending between the pair of said plurality of terminals;

instructions for calculating a slack time as a function of said net delay and said timing constraints;

instructions for displaying on the display screen said slack time in a spreadsheet format; and

instructions for creating at least one hyperlink between information within said floorplan and information within said spreadsheet.

22. The media as recited in claim 21, further comprising:

instructions for displaying on the display screen in said spreadsheet said timing constraints.

23. The media as recited in claim 21, further comprising:

instructions for displaying on the display screen in said spreadsheet said net delay.

24. The media as recited in claim 21, further comprising:

instructions for displaying said floorplan on said display screen; and

instructions for displaying said signal path on the floorplan on the display screen in response to user input.

25. The media as recited in claim 21, further comprising:

instructions for selecting at least one signal path of said integrated circuit in response to user input;

wherein said instructions for calculating a slack time comprises instructions for calculating slack times for said at least one signal path selected.

26. The media as recited in claim 21, further comprising:

instructions for displaying on the display screen in said spreadsheet source and destination terminal identifiers associated with said signal path.

27. An integrated circuit having a floorplan designed using a computer-implemented method, wherein said method is performed on a computer system comprising a display screen, an input device, and a processor, the method comprising:

receiving a floorplan comprising elements of an integrated circuit arranged across a layout space, said floorplan includes a plurality of nets which extend between a plurality of terminals arranged at specified coordinates within said physical layout space;

receiving timing constraints for at least a pair of said plurality of terminals;

calculating a net delay for a signal path, wherein said signal path comprises a portion of one of said plurality of nets, said portion extending between the pair of said plurality of terminals;

calculating a slack time as a function of said net delay and said timing constraints;

displaying on the display screen said slack time in a spreadsheet format; and

creating at least one hyperlink between information within said floorplan and information within said spreadsheet.

28. The circuit as recited in claim 27, wherein said method further comprises:

displaying on the display screen in said spreadsheet said timing constraints.

29. The circuit as recited in claim 27, wherein said method further comprises:

displaying on the display screen in said spreadsheet said net delay.

30. The circuit as recited in claim 27, wherein said method further comprises:

displaying on the display screen in said spreadsheet source and destination terminal identifiers associated with said signal path.

31. The circuit as recited in claim 27, wherein said method further comprises:

displaying said floorplan on said display screen; and

displaying said signal path on the floorplan on the display screen in response to user input.

32. The circuit as recited in claim 27, wherein said method further comprises:

selecting at least one signal path of said integrated circuit in response to user input;

wherein said calculating a slack time comprises calculating slack times for said at least one signal path selected.