High-throughput interconnect allowing bus transactions based on partial access requests

• US 5,911,051 A
• Filed: 09/27/1996
• Issued: 06/08/1999
• Est. Priority Date: 03/29/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Baxter, Brent S., Langendorf, Brian K., Case, Colyn, Meinerth, Kim A., Carson, David G., Hayek, George R.
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Etienne, Ario
• Application Number:
  US08/721,686
• Time in Patent Office: 984 Days
• Field of Search: 395/287, 395/856, 395/728
• US Class Current: 710/107
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G06F 13/1631 through address comparison

Abstract

A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target. If such segment or segments have changed since the previous access request, then they are provided to the target only for purposes of updating state in the target. Access requests may optionally be provided to the target on a separate port from the port used to transmit data in response to access requests.

Claims

1. A method of performing a bus transaction, the bus transaction including an access request for requesting a data transfer on a bus, the access request having a plurality of bits, the method comprising:

determining whether particular bits of the access request are different from corresponding bits of a previous access request; and

requesting the data transfer by transmitting only a first subset of the plurality of bits to a target based on said determining, the first subset consisting of less than all of the bits of the access request.

2. A method according to claim 1, wherein the access request includes a second subset of the plurality of bits, the second subset consisting of the bits not included in the first subset, wherein the method further comprises initiating the data transfer in response to receiving the first subset and not the second subset.

3. A method according to claim 2, wherein said initiating the data transfer comprises accessing a location in a memory.

4. A method according to claim 1, further comprising:

transmitting a second subset of the plurality of bits of the access request to the target device;

storing the second subset in a register in the target device to update the register, the second subset consisting of the bits of the access request not included in the first subset; and

using the target device to perform the data transfer based on the first subset and the contents of the register.

5. A method of performing a bus transaction, the bus transaction including a data transfer and an access request for requesting the data transfer, the method comprising:

separating the access request into a plurality of subsets, the plurality of subsets including a first subset and a second subset;

determining whether the second subset is different from a corresponding second subset of a previous access request;

transmitting the first subset to a target device to initiate the bus transaction; and

transmitting the second subset to the target device only if the second subset is different from the corresponding second subset of the previous access request.

6. A method according to claim 5, further comprising initiating the data transfer in response to receiving only the first subset of the access request, wherein the first subset and the second subset are mutually exclusive.

7. A method according to claim 6, wherein said initiating the data transfer comprises accessing a location in a memory.

8. A method according to claim 5, wherein the access request includes a plurality of control bits and a plurality of address bits, the first subset of the access request including a subset of the control bits and a subset of the address bits, the second subset of the access request including a subset of the address bits.

9. A method according to claim 5, wherein the second subset of the access request includes a third subset, the method further comprising:

determining whether the third subset is different from a corresponding third subset of the previous access request; and

transmitting the third subset to the target device only if the third subset is different from the corresponding third subset of the previous access request.

10. A method according to claim 9, wherein the access request includes a command bit, a length bit, and a plurality of address bits, the first subset of the access request including the length bit and a first subset of the address bits, the second subset of the access request including the command bit and a second subset of the address bits, the third subset of the access request including a third subset of the address bits.

11. A method according to claim 5, further comprising storing the corresponding second subset of the previous access request in a register in the target device;

and

if the second subset is different from the corresponding second subset of the previous access request, using the second subset to update the contents of the register.

12. A method of performing a bus transaction, the bus transaction including an access request for requesting a data transfer, the method comprising:

separating the access request into a plurality of subsets, the plurality of subsets including a first subset and a second subset;

using only the first subset of the access request to initiate the bus transaction; and

providing the second subset of the access request to a target device only to update state in the target device.

13. A method according to claim 12, wherein said providing the second subset of the access request to the target device comprises providing the second subset of the access request to the target device only if the second subset is different from a corresponding second subset of a previous access request.

14. A method according to claim 12, further comprising storing the corresponding second subset of the previous access request in a register in the target device, wherein said providing the second subset of the access request to the target device only to update state in the target device comprises:

using the second subset to update the contents of the register if the second subset is different from a corresponding second subset of the previous access request.

15. A method according to claim 12, wherein said using only the first subset of the access request to initiate the bus transaction comprises accessing a location in a memory.

16. A method according to claim 12, wherein the access request includes a plurality of control bits and a plurality of address bits, the first subset of the access request including a subset of the control bits and a subset of the address bits, the second subset of the access request including a subset of the address bits.

17. A method according to claim 12, wherein the access request includes a command bit, a length bit, and a plurality of address bits, the first subset of the access request including the length bit and a first subset of the address bits, the second subset of the access request including the command bit and a second subset of the address bits.

18. In a device operable as a bus agent in a computer system, a method of enabling bus transactions to be performed, each bus transaction including an access request for requesting a corresponding data transfer, each access request including a plurality of bits, the method comprising the steps of:

providing a first transaction mode in which a target of each bus transaction receives all of said plurality of bits of an access request on a bus to perform a corresponding data transfer on the bus; and

providing a second transaction mode in which a target of a bus transaction can perform a data transfer on the bus in response to receiving only a first subset of the plurality of bits of a corresponding access request at a sideband port, the first subset consisting of less than all of said plurality of bits of the corresponding access request.

19. A method according to claim 18, wherein, in the step of providing the second transaction mode, the corresponding access request includes a second subset that is mutually exclusive of the first subset, and wherein the target initiates a data transfer in response to receiving only the first subset of the plurality of bits if the second subset matches a corresponding second subset of a previous access request.

20. A method according to claim 19, wherein said first subset comprises a plurality of low order address bits and a plurality of length bits of the corresponding access request.

21. A device operable as a target of a bus operation, the device comprising:

first logic for performing a first data transfer in response to receiving a first access request on a bus by communicating a first set of data on the bus; and

second logic for performing a second data transfer in response to receiving a second access request, the second access request including a first segment and a second segment, the second logic receiving the first segment of the second access request at a sideband port, the second logic further for communicating a second set of data on the bus in response to receiving only the first segment of the second access request.

22. A device according to claim 21, wherein the second logic comprises logic for initiating the second data transfer in response to the first segment of the second access request when the second segment of the second access request matches a corresponding segment of a previous access request.

23. A device according to claim 21, wherein the second logic comprises a register for storing the second segment, logic for receiving the second segment at the sideband port, logic for updating contents of the register based on the second segment, and logic for accessing a memory location based on the first segment and the contents of the register.

24. A device according to claim 21, wherein the second access request comprises a plurality of address bits, a plurality of length bits, and a plurality of command bits, and wherein the first segment comprises the length bits and a lower order subset of the address bits.

25. A device operable as a bus master in a processing system, the device comprising:

means for transmitting a first subset of an access request to a target device on a first set of signal lines, the access request for requesting a transfer of data;

means for determining whether a second subset of the access request is different from a corresponding second subset of a previous access request;

means for transmitting the second subset of the access request to the target device on the first set of signal lines only if the second subset is different from the corresponding second subset of the previous access request; and

means for transferring the data on a second set of signal lines.

26. A device according to claim 25, wherein the data transfer comprises a memory access.

27. A device according to claim 25, wherein the access request comprises a plurality of address bits, and wherein the first subset comprises a lower order subset of the address bits.

28. A device operable to perform transactions on a bus in a processing system, the bus including a set of address/data lines, the device comprising:

first logic coupled to the address/data lines and configured to transmit addresses of a first transfer mode to a target device on the address/data lines and to communicate data corresponding to the addresses of the first transfer mode with the target device on the address/data lines;

second logic coupled to a set of sideband address lines and configured to transmit addresses of a second transfer mode to a target device on the sideband address lines, wherein data corresponding to the addresses of the second transfer mode are communicated with the target device on the address/data lines, the second logic including;

means for transmitting a first subset of an address of the second transfer mode to a target device on the sideband address lines;

means for determining whether a second subset of the address of the second transfer mode differs from a corresponding second subset of a previous address; and

means for transmitting the second subset to the target device on the sideband address lines only if the second subset differs from the corresponding second subset of the previous address.

29. A device according to claim 28, wherein the address/data lines are capable of transmitting a first number of bits in parallel, and wherein the sideband address lines are capable of transmitting a second number of bits in parallel, the second number smaller than the first number.

30. A processing system comprising:

a processor;

a memory coupled to the processor;

a bus coupled to the processor and the memory; and

a device coupled to the bus and operable as a bus master, wherein the device is configured to;

transmit a first subset of an access request to a target device, the access request for requesting a transfer of data on the bus;

transmit a second subset of the access request to the target device only if the second subset is different from a corresponding second subset of a previous access request; and

communicate the data with the target device on the bus in response to transmitting the first subset and not the second subset of the access request to the target device.

31. A processing system according to claim 30, wherein the bus includes a plurality of address/data lines for transferring addresses and data, and wherein the device is further configured to transmit the first subset of the access request to the target device on a set of sideband address lines separate from the address/data lines.

32. A processing system according to claim 31, wherein the device is further configured to communicate the data with the target device on the address/data lines in response to transmitting the first subset of the access request to the target device on the set of sideband address lines.

33. A computer system comprising:

a processor;

a memory controller coupled to the processor;

a memory coupled to the memory controller;

a bus coupled to the memory controller, the bus including a set of address/data lines;

a device coupled to the bus and operable as a bus master to transmit memory access requests to the memory controller, the device further coupled to the memory controller by a set of sideband address lines, the device including;

first logic coupled to the address/data lines and configured to transmit access requests of a first transfer mode onto the address/data lines and to communicate data corresponding to the access requests of the first transfer mode on the address/data lines;

second logic coupled to the sideband address lines and configured to transmit access requests of a second transfer mode on the sideband address lines, wherein data corresponding to the access requests of the second transfer mode are communicated on the address/data lines, the second logic including;

means for transmitting a first subset of an access request of the second transfer mode on the sideband address lines;

means for determining whether a second subset of the access request of the second transfer mode differs from a corresponding second subset of a previous access request; and

means for transmitting the second subset on the sideband address lines as part of the access request of the second mode only if the second subset differs from the corresponding second subset of the previous access request.

34. A computer system according to claim 33, wherein the address/data lines comprise a first number of signal lines, and wherein the sideband address lines comprise a second number of signal lines, the second number smaller than the first number.