Method and apparatus for testing software

• US 5,911,059 A
• Filed: 12/18/1996
• Issued: 06/08/1999
• Est. Priority Date: 12/18/1996
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Applied Microsystems Corporation
• Inventors: Profit, Jack H. Jr.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Phan, Thai
• Application Number:
  US08/768,813
• Time in Patent Office: 902 Days
• Field of Search: 364/232.3, 364/221, 364/240, 364/240.5, 364/241.2, 364/264, 364/264.3, 364/267, 364/270, 364/DIG. 1, 364/926.9, 364/926.91, 364/578, 364/489, 364/490, 395/500, 395/568, 395/559, 395/551, 395/183.1, 395/183.13, 395/183.15, 395/185.03, 395/185.04, 395/185.08, 395/185.09, 395/183.22 , 395/183.06, 395/200.62, 395/200.48, 371/5.4, 371/22.1, 371/22.4, 371/21.3, 371/62, 371/22.3
• US Class Current: 703/23
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/3632 of specific synchronisation aspects
• CPC Class Codes: G06F 11/3652 in-circuit-emulation [ICE] arrangements
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software

Abstract

A system for testing and analyzing electronic systems, including a target processor and simulated target circuitry, and an associated target program to be executed on the target microprocessor. The system includes a processor emulator employing a hardware device for emulating the target microprocessor. The processor emulator has a memory for storing a plurality of computer instructions, including the target program and associated data. The processor emulator communicates with the memory to receive computer instructions from the memory and to access program specific data structures. The system further includes a hardware simulator adapted to simulate the target circuitry. A communications interface controls communication between the processor emulator and the hardware simulator. The processor emulator communicates with the hardware simulator using the communications interface when an event requires interaction of the target program with the target circuitry. A synchronization circuit contained in the communications interface synchronizes the processor emulator and the hardware simulator at a time other than when an event requires interaction of the target program with the target circuitry.

Claims

1. A system for testing and analyzing electronic systems, including a target microprocessor and simulated target circuitry, and an associated target program to be executed on the target microprocessor, comprising:

a processor emulator employing a hardware device for emulating the target microprocessor, the processor emulator having a memory for storing a plurality of computer instructions, the computer instructions including the target program and the processor emulator communicating with the memory to receive computer instructions from the memory;

a hardware simulator adapted to simulate the target circuitry; and

a communications interface to control communication between the processor emulator and the hardware simulator, the processor emulator communicating with the hardware simulator using the communications interface when an event requires interaction of the target program with the target circuitry, the communications interface further including a synchronization circuit which synchronizes the processor emulator and the hardware simulator at a time other than when an event requires interaction of the target program with the target circuitry.

2. The system of claim 1 wherein the synchronization circuit periodically synchronizes the processor emulator and the hardware simulator.

3. The system of claim 2 wherein the synchronization circuit synchronizes the processor emulator and the hardware simulator at constant periods.

4. The system of claim 1 wherein the times at which the synchronization circuit synchronizes the processor emulator and the hardware simulator are determined in response to computer instructions contained in the target program.

5. The system of claim 1 wherein the processor emulator is coupled to the hardware simulator by a computer network connection, the communications interface controlling communications over the network.

6. The system of claim 1 wherein the communications interface comprises a target bus watch circuit to detect an event requiring the target program to interact with the target circuitry.

7. The system of claim 6 wherein the target bus watch circuit temporarily halts execution of the plurality of computer instructions while the hardware simulator processes the event requiring the target program to interact with the target circuitry.

8. The system of claim 1 wherein the communications interface comprises a dedicated, low latency communications channel.

9. The system of claim 1 wherein the event requiring the target program to interact with the target circuitry is an input/output(I/O) instruction to the hardware simulator, and the communication interface controls communication of the I/O instruction from the processor emulator to the hardware simulator.

10. The system of claim 1 wherein the processor emulator comprises a microprocessor emulator with the memory integrated therein, the integrated memory containing the computer instructions and associated data structures.

11. The system of claim 1 wherein the processor emulator is a hardware circuit emulator with the memory integrated therein, the integrated memory containing the computer instructions and associated data structures.

12. The system of claim 1, further including a computer communicating with the processor emulator, the computer also executing the hardware simulator.

13. A system for testing and analyzing electronic systems, including a target microprocessor and simulated target circuitry, and an associated target program to be executed on the target microprocessor, comprising:

a processor emulator including the target processor and a memory for storing data and a plurality of computer instructions, including the target program, the target processor communicating with the memory over a target bus to receive computer instructions from the memory, the target bus containing address, data, and status information;

a hardware simulator adapted to simulate the target circuitry, the hardware simulator providing a HOST INTERRUPT signal when the target circuitry needs access to the target program;

a target bus watch circuit coupled to the target bus of the processor emulator which detects when an event requires interaction of the target program with the target circuitry and in response to detecting such an event outputs a TBW INTERRUPT signal;

a simulation time keeper circuit which periodically generates a STK INTERRUPT signal; and

a communications controller which controls communication between the processor emulator and the hardware simulator in response to the HOST INTERRUPT, TBW INTERRUPT, and STK INTERRUPT signals, the communications controller synchronizing the processor emulator and the hardware simulator when the communications controller receives at least one of the TBW INTERRUPT signal and the STK INTERRUPT signal.

14. The system of claim 13 wherein the target bus watch circuit comprises:

a memory latch array which stores information indicative of the address range in which the data and computer instructions are stored in the memory;

a comparator circuit which compares target address information on the target bus to the information indicative of the address range stored in the memory latch array and provides an output signal when the target address is outside the address range; and

a RUN/HALT controller coupled to the output signal from the comparator circuit which in response to that output signal provides the TBW INTERRUPT signal and further provides a RUN/HALT signal to the processor emulator which causes the target processor to halt execution of the target program, the RUN/HALT controller further providing the RUN/HALT signal to the processor emulator in response to the STK INTERRUPT signal from the simulation time keeper circuit.

15. The system of claim 14 wherein the RUN/HALT controller comprises:

a dual-ported address latch having one port coupled to the target address bus of the processor emulator and the other port coupled to the communications controller;

a dual-ported data latch having one port coupled to the target data bus of the processor emulator and the other port coupled to the communications controller;

a dual-ported status latch having one port coupled to the target status bus of the processor emulator and the other port coupled to the communications controller;

a latch control circuit which controls the latching of data by the dual-ported address latch, the dual-ported data latch, and the dual-ported status latch, the latch control circuit being controlled by the communications controller to allow the communications controller to send address, data, and status information to the hardware simulator and interrupt information from the hardware simulator to the processor emulator; and

a target processor state machine adapted for the specific target processor which provides the RUN/HALT signal and the TBW INTERRUPT signal, the communications controller controlling the target processor state machine so that the target processor state machine releases the processor emulator to continue execution of the target program after the controller has synchronized the processor emulator and the hardware simulator.

16. The system of claim 14 wherein the comparator circuit comprises a plurality of pairs of comparator logic circuits to determine whether a specific target address is outside the address range stored in the memory latch array, the address range including a lower address value and an upper address value, and each pair of comparator logic circuits comprising:

a first comparator logic circuit which provides a true output when the specific target address is greater than or equal to the lower address value;

a second comparator logic circuit which provides a true output when the specific target address is less than or equal to the upper address value; and

a logical AND circuit having as its inputs the outputs from the first and second comparator logic circuits and providing a true output when both the outputs from the first and second comparator logic circuits are true.

17. The system of claim 16 wherein the output from each AND circuit associated with each pair of the comparator logic circuits is connected to an input of an OR logic circuit and an output from the OR circuit provides the output signal from the comparator circuit.

18. The system of claim 14 wherein the memory latch array and the comparator circuit are implemented in a fast memory array and combinatorial logic, respectively.

19. The system of claim 13 wherein the simulation time keeper circuit comprises a one-shot programmable interval timer.

20. A method for testing and analyzing electronic systems, such systems including a target microprocessor and simulated target circuitry, and an associated target program to be executed on the target microprocessor, comprising the steps of:

storing a plurality of computer instructions in a memory, the computer instructions including the target program;

emulating the target microprocessor using a processor emulator hardware device, the processor emulator communicating with the memory to receive computer instructions from the memory;

simulating the target circuitry using a hardware simulator;

controlling communication between the processor emulator and the hardware simulator, the processor emulator communicating with the hardware simulator when an event requires interaction of the target program with the target circuitry; and

synchronizing the processor emulator and the hardware simulator at a time other than when an event requires interaction of the target program with the target circuitry.

21. The method of claim 20 wherein the step of synchronizing the processor emulator and the hardware simulator periodically synchronizes the processor emulator and the hardware simulator.

22. The method of claim 21 wherein the step of synchronizing the processor emulator and the hardware simulator synchronizes the processor emulator and the hardware simulator at constant periods.

23. The method of claim 20 wherein the times at which the synchronization circuit synchronizes the processor emulator and the hardware simulator are determined in response to computer instructions contained in the target program.

24. The method of claim 20 wherein the step of controlling communication includes the step of communicating over a computer network connection.

25. The method of claim 20 wherein the step of controlling communication includes the step of communicating over a dedicated low latency communications channel.

26. The method of claim 20 wherein the step of controlling communication includes the step of detecting an event requiring the target program to interact with the target circuitry.

27. The method of claim 26 wherein the step of detecting includes the step of halting temporarily the execution of the plurality of computer instructions while the hardware simulator processes the event requiring the target program to interact with the target circuitry.

28. The method of claim 26 wherein the event requiring the target program to interact with the target circuitry is an input/output(I/O) instruction to the hardware simulator, and the step of controlling communication controls communication of the I/O instruction from the processor emulator to the hardware simulator.

29. The method of claim 20 wherein the step of emulating the target microprocessor includes the step of using a microprocessor emulator coupled to a memory device, the memory device containing data and the computer instructions.

30. The method of claim 20 wherein the step of emulating the target microprocessor includes the step of using a hardware circuit emulator coupled to a memory device, the memory device containing data and the computer instructions.

31. The method of claim 20, further including the step of using a computer to communicate with the processor emulator, the computer also executing the hardware simulator.

32. An apparatus for synchronizing a processor emulator and a hardware simulator, the processor emulator including a target program and the hardware simulator including a simulation of a target circuit, comprising:

a communications interface to control communication between the processor emulator and the hardware simulator, the communications interface providing communication between the processor emulator and the hardware simulator when an event requires interaction of the target program with the target circuitry; and

a synchronization circuit coupled to the communications interface which synchronizes the processor emulator and the hardware simulator at a time other than when an event requires interaction of the target program with the target circuitry.

33. The apparatus of claim 32 wherein the synchronization circuit periodically synchronizes the processor emulator and the hardware simulator.

34. The apparatus of claim 33 wherein the synchronization circuit synchronizes the processor emulator and the hardware simulator at constant periods.

35. The apparatus of claim 32 wherein the times at which the synchronization circuit synchronizes the processor emulator and the hardware simulator are determined in response to computer instructions contained in the target program.