System and method for accessing peripheral devices on a non-functional controller

• US 5,911,084 A
• Filed: 02/17/1998
• Issued: 06/08/1999
• Est. Priority Date: 10/07/1994
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Lory, Jay, Jones, Craig S., Pecone, Victor K.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US09/024,719
• Time in Patent Office: 476 Days
• Field of Search: 395/821-894, 395/280-286
• US Class Current: 710/62
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0781 Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/3476 Data logging G06F11/14, G06F11/2205 take precedence

Abstract

A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.

Claims

1. A computer system which enables host access to peripheral device memories on a non-functioning bus adapter, comprising:

a CPU;

a first bus coupled to the CPU;

a bus adapter coupled to said first bus which performs a function, said bus adapter comprising;

a bus interface coupled to said first bus;

a second bus coupled to said bus interface;

a local processor coupled to said second bus;

a peripheral bus coupled to said bus interface; and

one or more peripheral device memories coupled to said peripheral bus; and

a jumper coupled to said bus interface in said bus adapter which is operable in a first position to map said one or more peripheral device memories to said bus interface wherein said one or more peripheral device memories are accessible by said CPU when said bus adapter is non-functioning, and is operable in a second position to map said one or more peripheral device memories to be accessible by said local processor comprised in said bus adapter;

wherein said CPU accesses said one or more peripheral device memories when said jumper is in said first position.

2. The computer system of claim 1, wherein said bus interface comprises:

a first bus interface coupled to said first bus;

a second bus interface coupled to said first bus interface and said second bus; and

a peripheral bus interface coupled to said first bus interface and said second bus interface, wherein said peripheral bus is coupled to said peripheral bus interface.

3. The computer system of claim 2, wherein said CPU accesses said first bus interface, and wherein said first bus interface accesses said one or more peripheral device memories in response to said CPU accessing said first bus interface.

4. The computer system of claim 1, wherein said local processor is inoperable during operation of said CPU accessing said one or more peripheral device memories.

5. The computer system of claim 1, wherein said second bus is inaccessible during operation of said CPU accessing said one or more peripheral device memories.

6. The computer system of claim 1, wherein said CPU accesses said one or more peripheral device memories without accessing said second bus.

7. The computer system of claim 1, wherein said bus adapter is inoperable during operation of said CPU accessing said one or more peripheral device memories.

8. The computer system of claim 1, wherein said one or more peripheral device memories comprise one or more Flash memories storing boot and initialization code for said bus adapter;

and

wherein said CPU writes new data to said one or more Flash memories.

9. The computer system of claim 1, wherein said one or more peripheral device memories comprise one or more non-volatile random access memories;

and

wherein said CPU reads failure data from said one or more non-volatile random access memories.

10. The computer system of claim 1, wherein said first and said second buses comply with a peripheral component interconnect (PCI) bus standard.

11. A computer system comprising:

a CPU;

a first bus coupled to the CPU;

a bus adapter coupled to the first bus, the bus adapter including

a bus interface coupled to said first bus;

a second bus coupled to said bus interface;

a local processor coupled to said second bus;

a peripheral bus coupled to said bus interface; and

a memory coupled to said peripheral bus;

means for configuring the memory to map to the bus interface, wherein the memory is accessible by the CPU when the memory is mapped to the bus interface;

means for beginning a CPU startup routine, wherein the CPU detects the memory coupled to the peripheral bus as being mapped to the bus interface;

means for accessing the memory by the CPU after the CPU start up routine;

means for reconfiguring the memory to unmap the memory from the bus interface after the CPU accessing the memory, wherein the memory is accessible to the local processor comprised in the bus adapter in response to the reconfiguring; and

means for the CPU restarting after the reconfiguring the memory.

12. The computer system of claim 11, wherein the bus interface comprises:

a first bus interface for coupling to the first bus;

a second bus interface coupled to the first bus interface and the second bus; and

a peripheral bus interface coupled to the first bus interface and the second bus interface, wherein the peripheral bus is coupled to the peripheral bus interface; and

wherein

the means for accessing the memory by the CPU includes means for accessing the first bus interface by the CPU, wherein the first bus interface accesses the memory in response to the CPU accessing the first bus interface.

13. The computer system of claim 11, wherein the means for accessing the memory by the CPU is operable when the local processor is inoperable.

14. The computer system of claim 11, wherein the means for accessing the memory by the CPU is operable when the second bus is inaccessible.

15. The computer system of claim 11, wherein the means for accessing the memory by the CPU comprises means for accessing the memory without accessing the second bus.

16. The computer system of claim 11, wherein the means for accessing the memory by the CPU is operable when the bus adapter is inoperable.

17. The computer system of claim 11, wherein

the memory is Flash memory storing boot and initialization code for the bus adapter;

and

the means for accessing the memory by the CPU comprises means for writing new data to the Flash memory.

18. The computer system of claim 11, wherein

the memory is non-volatile random access memory;

and

the means for accessing the memory by the CPU comprises means for reading failure data from the non-volatile random access memory.

19. The computer system of claim 11, wherein the means for configuring the memory comprises a jumper.

20. The computer system of claim 11, wherein the first and the second buses comply with a peripheral component interconnect (PCI) bus standard.

21. The computer system of claim 11, wherein the bus adapter is a small computer systems interface adapter.