Method of forming a contact hole in an interlevel dielectric layer using dual etch stops
DC CAFCFirst Claim
1. A method of forming a contact hole in an interlevel dielectric layer using dual etch stops, comprising:
- providing a semiconductor substrate;
forming a gate over the substrate,forming a source/drain region in the substrate;
providing a source/drain contact electrically coupled to the source/drain region;
forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact;
forming an etch mask over the interlevel dielectric layer;
applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer;
applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact; and
applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide a contact hole in the interlevel dielectric layer.
2 Assignments
Litigations
6 Petitions
Accused Products
Abstract
A method of forming a contact hole in an interlevel dielectric layer using dual etch stops includes the steps of providing a semiconductor substrate, forming a gate over the substrate, forming a source/drain region in the substrate, providing a source/drain contact electrically coupled to the source/drain region, forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact, forming an etch mask over the interlevel dielectric layer, applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer, applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact, and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide the contact hole. In this manner, the contact hole is formed in the interlevel dielectric without any appreciable gouging of the underlying materials.
-
Citations
30 Claims
-
1. A method of forming a contact hole in an interlevel dielectric layer using dual etch stops, comprising:
-
providing a semiconductor substrate; forming a gate over the substrate, forming a source/drain region in the substrate; providing a source/drain contact electrically coupled to the source/drain region; forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact; forming an etch mask over the interlevel dielectric layer; applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer; applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact; and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide a contact hole in the interlevel dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method of forming a contact hole in an interlevel dielectric layer using dual etch stops, comprising:
-
providing a semiconductor substrate; forming a gate insulator over the substrate; forming a gate on the gate insulator; forming a source/drain region in the substrate; providing a source/drain contact electrically coupled to the source/drain region; forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact, including forming the first dielectric layer on the second dielectric layer and forming the second dielectric layer on the third dielectric layer, wherein the gate has a greater thickness than a combined thickness of the second and third dielectric layers; forming an etch mask over the interlevel dielectric layer; applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer; applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact; and applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide a contact hole in the interlevel dielectric layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
-
21. A method of forming a contact hole in an interlevel dielectric layer using dual etch stops, comprising the sequence set forth:
-
providing a semiconductor substrate; forming a gate oxide over the substrate; forming a polysilicon gate on the gate oxide; forming a source/drain region in the substrate and providing a source/drain contact electrically coupled to the source/drain region, wherein a distance between a top surface of the polysilicon gate and the substrate is greater than a distance between a top surface of the source/drain contact and the substrate; forming an interlevel dielectric layer that consists of first, second and third dielectric layers over the source/drain contact, including forming the first dielectric layer on the second dielectric layer, forming the second dielectric layer on the third dielectric layer, and forming the third dielectric layer on the source/drain contact, wherein the first and third dielectric layers are the same material, the polysilicon gate has a greater thickness than a combined thickness of the second and third dielectric layers, and the first dielectric layer has a greater thickness than the polysilicon gate; forming a photoresist layer on the interlevel dielectric layer; applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the photoresist layer using the photoresist layer as an etch mask and the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer; applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the photoresist layer using the photoresist layer as an etch mask and the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact; and applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the photoresist layer using the photoresist layer as an etch mask, thereby forming a third hole through the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide a contact hole with straight sidewalls in the interlevel dielectric layer. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
-
Specification