High voltage driver circuit with diode

• US 5,912,495 A
• Filed: 07/31/1996
• Issued: 06/15/1999
• Est. Priority Date: 07/31/1995
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Novelli, Aldo, Depetro, Riccardo
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/690,060
• Time in Patent Office: 1,049 Days
• Field of Search: 257/355, 257/500, 257/577, 257/531, 257/539, 257/582, 257/603, 257/547, 257/544, 257/546, 257/550, 257/570, 257/551, 257/362
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7817 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

The invention relates to a structure for and the method of manufacturing a driver circuit for an inductive load monolithically integrated on a semiconductor substrate doped with a first type of doping agent and on which is grown an epitaxial well having a second type of doping agent. An insulated well doped with the same type of doping agent as the substrate, which houses at least one power transistor of the driver circuit, is provided within the epitaxial well. The epitaxial well also houses a first and a second active area which house the cathode terminal and anode terminal of a protection diode, respectively.

Claims

1. A driver circuit, for an inductive load, monolithically integrated on a semiconductor substrate doped with a first type of doping agent and on which is grown an epitaxial well, bounded by insulating regions, which has a second type of doping agent and in which is provided a further well housing at least one power transistor of the driver circuit, characterised in that said epitaxial well also houses a first and a second active region which house respectively the cathode terminal and the anode terminal of a protection diode connected to said transistor and which is provided with a buried region between the substrate and the epitaxial well in proximity of said active regions.

2. The driver circuit of claim 1 wherein that said first active region also houses the drain terminal of the power transistor.

3. The driver circuit of claim 1 wherein said buried region is doped with the second type of doping agent.

4. The driver circuit of claim 3 wherein said buried region has a greater amount of the second type of doping agent in comparison with the epitaxial well.

5. A driver circuit for an inductive load, comprising:

a semiconductor layer;

a well disposed within the semiconductor layer;

a diode disposed within the well, the diode having an anode and a cathode, the anode being coupled to the load, the diode operable to limit the turning on of a parasitic transistor; and

a transistor disposed in the well, the transistor coupled between the diode and a reference voltage, the transistor operable to receive a control signal, and to couple the load to the reference voltage through the diode responsive to the control signal having a first state.

6. The driver circuit of claim 5, further comprising:

a buried region disposed in the semiconductor layer in the approximate vicinity of the diode, the buried region operable to be a barrier to carrier injection in the semiconductor layer or to the well.

7. The driver circuit of claim 6 wherein the buried region includes a doped semiconductor material.

8. The driver circuit of claim 5 wherein the semiconductor layer includes an epitaxial layer overlaying a substrate.

9. The driver circuit of claim 5 wherein the reference voltage is ground.

10. The driver circuit of claim 5 wherein the transistor has a gate, a source, and a drain, the drain being coupled to the cathode of the diode, the source operable to be coupled to the reference voltage, and the gate operable to receive the control signal.

11. A driver circuit for an inductive load, comprising:

a substrate;

an epitaxial layer disposed over the substrate;

a first well disposed within the epitaxial layer;

a second well disposed within the first well;

a first active region disposed within the first well;

a second active region disposed within the first well;

a diode having an anode and a cathode, the cathode disposed in the first active region, and the anode disposed in the second active region, the diode being coupled to the load, the diode operable to limit the turning on of a parasitic transistor;

a transistor disposed at least in part within the second well, the transistor having a gate, a source, and a drain, the transistor operable to be coupled between a reference voltage and the diode, the transistor operable to receive a control signal and to couple the diode to the reference voltage responsive to the control signal; and

a buried region disposed adjacent the locations where the substrate and the epitaxial layer meet, the buried region being disposed in the proximity of the first and second active regions.

12. The driver circuit of claim 11 wherein the first active region comprises a semiconductor material doped with a relatively high concentration of a first type of doping agent and the second active region comprises a semiconductor material doped with a relatively high concentration of a second type of doping agent.

13. The driver circuit of claim 12 wherein the first type of doping agent comprises an N-type doping agent, and the second type of doping agent comprises a P-type doping agent.

14. The driver circuit of claim 11 wherein the source of the transistor is operable to be coupled to the reference voltage, the drain is coupled to the cathode of the diode, and the gate is operable to receive the control signal.

15. The driver circuit of claim 11 wherein the cathode of the diode is coupled to the drain of the transistor and the anode is operable to be coupled to the load.

16. The driver circuit of claim 11 wherein the drain of the transistor is disposed within the first active region.

17. The driver circuit of claim 11 wherein the reference voltage comprises ground.

18. The driver circuit of claim 11, further comprising:

a third well disposed on the substrate, the third well being approximately adjacent to the first well; and

an insulating region disposed between the first well and the third well, the insulating region electrically insulating the first well from the third well.

19. The driver circuit of claim 11 wherein the substrate comprises a semiconductor material doped with a first type of doping agent, the first well comprises a semiconductor material doped with a second type of doping agent, and the buried region comprises a semiconductor material doped with the second type of doping agent, the buried region having a greater amount of the second doping material than the first well.