Methods, circuits and devices for improving crossover performance and/or monotonicity, and applications of the same in a universal serial bus (USB) low speed output driver

• US 5,912,569 A
• Filed: 09/22/1997
• Issued: 06/15/1999
• Est. Priority Date: 09/22/1997
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Alleven, Gary W.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/934,933
• Time in Patent Office: 631 Days
• Field of Search: 327/108, 327/112, 327/378, 327/379, 327/384, 327/389, 327/391, 326/26, 326/27, 326/82, 326/83, 326/87, 326/90, 326/91
• US Class Current: 327/108
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/00323 Delay compensation
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 5/151 with two complementary outputs

Abstract

A circuit comprising a first driver circuit, a second driver circuit and a delay circuit. The first driver circuit may be configured to generate a first output signal and a control signal in response to a first input signal. The delay circuit may be configured to generate a delay signal in response to a second input signal and the control signal. The second driver circuit may be configured to generate a second output signal in response to the delay signal.

Claims

1. A circuit comprising:

a first driver circuit configured to generate (i) a first output signal and (ii) a first control signal in response to a first input signal;

a delay circuit configured to generate a delay signal in response to (i) a second input signal and (ii) said first control signal; and

a second driver circuit configured to generate a second output signal in response to said delay signal, wherein said delay circuit adjusts a crossover point between said first and second output signals.

2. The circuit according to claim 1 wherein:

said first input signal comprises a first pair of complementary input signals; and

said second input signal comprises a second pair of complementary input signals.

3. The circuit according to claim 1 wherein said delay circuit comprises:

a comparator circuit configured to present a second control signal in response to (i) said first control signal and (ii) a threshold voltage; and

an output circuit configured to present said delay signal in response to said second control signal, wherein said threshold voltage controls said delay circuit.

4. The circuit according to claim 3 wherein said output circuit comprises a memory cell.

5. The circuit according to claim 4 wherein said memory cell comprises a flip-flop.

6. The circuit according to claim 5 wherein said flip-flop comprises a reset/set (R/S) flip-flop.

7. The circuit according to claim 3, wherein said first and second input signals are generated in response to a data input signal.

8. The circuit according to claim 7 wherein said delay circuit further comprises an enable circuit coupled between said comparator circuit and said output circuit to enable said delay signal in response to a transition of said second input signal.

9. A Universal Serial Bus driver comprising the circuit of claim 1.

10. A circuit comprising:

means for generating (i) a first output signal and (ii) a first control signal in response to a first input signal;

means for generating a delay signal in response to (i) a second input signal and (ii) said first control signal; and

means for generating a second output signal in response to said delay signal, wherein said delay circuit adjusts a crossover point between said first and second output signals.

11. The circuit according to claim 10 wherein said means for generating said delay signal further comprises:

comparator means for generating a second control signal in response to (i) said first control signal and (ii) a threshold voltage; and

means for generating said delay signal in response to said second control signal.

12. The circuit according to claim 11, wherein said means for generating said delay signal comprises means for enabling coupled between said comparator means and said output circuit means to enable said delay signal in response to a transition of said second input signal.

13. A Universal Serial Bus driver comprising the circuit of claim 10.

14. A method for delaying an output signal comprising the steps of:

generating first and second input signals;

generating a first control signal and a first output signal in response to said first input signal;

generating a delay signal in response to (i) said second input signal and (ii) said first control signal; and

generating a second output signal in response to said delay signal, wherein said delay signal adjusts a crossover point between said first and second output signals.

15. The method according to claim 14, wherein said generating a delay signal step further comprises:

comparing a threshold voltage with said first control signal to generate a second control signal; and

generating said delay signal in further response to said second control signal.

16. The method according to clam 14,

wherein said delay signal is generated in further response to said second input signal.