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Synchronizing clock pulse generator for logic derived clock signals with synchronous clock suspension capability for a programmable device

  • US 5,912,572 A
  • Filed: 03/28/1997
  • Issued: 06/15/1999
  • Est. Priority Date: 03/28/1997
  • Status: Expired due to Term
First Claim
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1. A circuit, comprising:

  • means for generating an asynchronous logic derived clock signal as a logical combination of a plurality of input signals using one or more logic gates; and

    means for synchronizing said asynchronous logic derived clock signal to a reference clock signal to generate a synchronized logic derived clock signal, said synchronized logic derived clock signal having a fixed duration logic HIGH interval for variable duration logic HIGH intervals of said one or more input signals.

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