Synchronizing clock pulse generator for logic derived clock signals with synchronous clock suspension capability for a programmable device
First Claim
1. A circuit, comprising:
- means for generating an asynchronous logic derived clock signal as a logical combination of a plurality of input signals using one or more logic gates; and
means for synchronizing said asynchronous logic derived clock signal to a reference clock signal to generate a synchronized logic derived clock signal, said synchronized logic derived clock signal having a fixed duration logic HIGH interval for variable duration logic HIGH intervals of said one or more input signals.
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Abstract
A programmable device includes a circuit for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input logic signals from which the synchronized logic derived clock signal is created. Further, the programmable device includes circuit for suspending a clock signal. In one embodiment, an asynchronous logic derived clock signal is generated and synchronized with a synchronous clock signal provided to the programmable device to produce a synchronized logic derived clock signal. The synchronized logic derived clock signal is logically combined with the synchronous clock signal to produce a suspended clock signal.
80 Citations
21 Claims
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1. A circuit, comprising:
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means for generating an asynchronous logic derived clock signal as a logical combination of a plurality of input signals using one or more logic gates; and means for synchronizing said asynchronous logic derived clock signal to a reference clock signal to generate a synchronized logic derived clock signal, said synchronized logic derived clock signal having a fixed duration logic HIGH interval for variable duration logic HIGH intervals of said one or more input signals. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of generating a synchronized logic derived clock signal in a programmable device comprising the steps of:
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generating an asynchronous logic derived clock signal as a logical combination of a plurality of input signals using one or more logic gates; and synchronizing said asynchronous logic derived clock signal to a reference clock signal to produce a synchronized logic derived clock signal having a fixed duration logic HIGH interval for variable duration logic HIGH intervals of said one or more input signals. - View Dependent Claims (9, 10)
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11. A method of synchronizing an asynchronous logic derived clock signal with a data signal in a programmable device comprising the steps of:
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capturing an input signal in said programmable device in response to a first clock pulse of a synchronous clock signal so as to produce said data signal; synchronizing said asynchronous logic derived clock signal with said synchronous clock signal to produce a synchronized logic derived clock signal having a fixed duration logic HIGH interval for variable duration logic HIGH intervals of said asynchronous logic derived clock signal; generating a suspended clock signal from said synchronous clock signal and said synchronized logic derived clock signal; and capturing said data signal in a register of said programmable device in response to said synchronized logic derived clock signal. - View Dependent Claims (12, 13, 14, 15)
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16. A programmable device, comprising:
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means for generating an asynchronous clock signal from one or more input signals; means for synchronizing said asynchronous clock signal to a reference clock signal to produce a synchronized logic derived clock signal coupled to said means for generating said asynchronous clock signal; and means for generating a suspended clock signal from said reference clock signal and said synchronized logic derived clock signal. - View Dependent Claims (17, 18, 19, 20)
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21. A method of saving power in a programmable device, comprising the steps of:
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producing a suspendable clock signal from a logical combination of a reference clock signal supplied to said programmable device and an asynchronous logic derived clock signal produced from one or more input signals to said programmable device, said suspendable clock signal being gated off and on in response to said input signals; and operating a register using said suspendable clock signal so that said register captures input signals presented on a data input of said register only when said suspendable clock signal is gated on and said suspendable clock signal is selected.
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Specification