MPEG decoder frame memory interface which is reconfigurable for different frame store architectures

• US 5,912,676 A
• Filed: 06/14/1996
• Issued: 06/15/1999
• Est. Priority Date: 06/14/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Malladi, Srinivasa R., Varansi, Surya, Amla, Vanya
• Primary Examiner(s): Chauhan, U.
• Application Number:
  US08/664,135
• Time in Patent Office: 1,096 Days
• Field of Search: 345/418, 345/302, 345/419, 345/433, 345/441-443, 345/501, 345/503, 345/520, 345/521, 345/526, 345/507-509, 345/511, 345/512, 345/515-518, 345/186, 345/188 , 345/191, 345/202, 345/203, 348/390, 348/400, 348/403, 348/420, 348/422, 348/714-721, 395/821, 395/823-825, 395/842, 395/843, 395/850, 395/853-855, 395/858, 395/859, 395/872, 711/1, 711/5, 711/100, 711/104-106, 711/147-153, 711/202, 711/209, 711/217, 711/218-220
• US Class Current: 345/531
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/433 characterised by techniques for memory access
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A frame memory interface architecture which is easily adaptable to interface to any of a plurality of frame memory storage architectures. In the preferred embodiment, the present invention comprises an MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes various slave devices which access a single external memory, wherein these slave devices include reconstruction logic or motion compensation logic, a reference frame buffer, display logic, a prefetch buffer, and host bitstream logic, among others. Each of the slave devices is capable of storing or retrieving data to/from the memory according to different frame storage formats, such as a scan line format, a tiled format, and a skewed tile format, among others. The frame memory interface is easily re-configurable to each of these different formats, thus providing improved efficiency according to the present invention. The slave device then generates a request to the memory controller. In response to the request, the memory controller reads the memory transfer values stored by the slave device and sets up an address generation process based on the memory transfer values. The memory controller then generates addresses to the memory according to this address generation process to perform the memory transfer based on the memory transfer values.

Claims

1. A method for performing a memory transfer operation in a system, wherein the system comprises a memory, a memory controller coupled to the memory, and at least one slave device coupled to the memory, the method comprising:

the slave device storing a plurality of memory transfer values to identify the transfer, wherein the plurality of values include a byte per row value indicating a number of bytes per row to be read/written, a skip bytes value indicating a number of bytes to be skipped in a row during the read/write transfer, and a number of rows value indicating the number of rows to be read/written in the transfer;

the slave device generating a request to the memory controller;

the memory controller reading said memory transfer values stored by the slave device; and

the memory controller generating addresses to the memory to perform the memory transfer based on said memory transfer values.

2. The method of claim 1, further comprising:

the memory controller setting up an address generation process based on said memory transfer values after the memory controller reads said memory transfer values stored by the slave device;

wherein the memory controller generates addresses to the memory to perform the memory transfer based on said address generation process.

3. The method of claim 1, wherein said slave device programming said memory transfer values further comprises the slave device programming a start address value indicating a page address and offset within the page of the memory where the memory transfer is to begin.

4. The method of claim 1, wherein said slave device programming the memory transfer values farther comprises the slave device programming a local start address value indicating a start address for buffers in said slave device where said data is to be read/written.

5. The method of claim 1, wherein said memory transfer operation comprises transferring an object having a non-rectangular shape, the method further comprising:

the slave device programming a left offset value and a right offset value, wherein said left offset value indicates a number of bytes to the left of a start address point and wherein said right offset value indicates a number of bytes to the right of the start address point; and

The slave device programming a left increment/decrement value and a right increment/decrement value, wherein said left increment/decrement value indicates an increasing/decreasing progression for a left side of the object, and wherein said right increment/decrement value indicates an increasing/decreasing progression for a right side of the object;

wherein said memory controller generating addresses to the memory to perform the memory transfer comprises the memory controller using said left and right offset values and said left increment/decrement and right increment/decrement values to generate said addresses to transfer said object having said non-rectangular shape.

6. The method of claim 1, further comprising:

one or more other devices generating request to the memory controller; and

the memory controller arbitrating among said requests to grant access to one of said slave devices.

7. The method of claim 1, wherein said slave device storing a plurality of memory transfer values to identify the transfer comprises the slave device storing a plurality of memory transfer values to identify a transfer of data according to a tiled format;

wherein the memory controller generating addresses to the memory to perform the memory transfer comprises the memory controller generating addresses to the memory to perform the memory transfer according to said tiled format based on said memory transfer values.

8. The method of claim 1, wherein said slave device storing a plurality of memory transfer values to identify the transfer comprises the slave device storing a plurality of memory transfer values to identify a transfer of data according to a raster scan format;

wherein the memory controller generating addresses to the memory to perform the memory transfer comprises the memory controller generating addresses to the memory to perform the memory transfer according to said raster scan format based on said memory transfer values.

9. The method of claim 1, wherein said slave device storing a plurality of memory transfer values to identify the transfer comprises the slave device storing a plurality of memory transfer values to identify a transfer of data according to a skewed tiled format;

wherein the memory controller generating addresses to the memory to perform the memory transfer comprises the memory controller generating addresses to the memory to perform the memory transfer according to said skewed tiled format based on said memory transfer values.

10. The method of claim 1, further comprising:

a first slave device storing a plurality of memory transfer values to identify a transfer of data according to a first format;

the first slave device generating a request to the memory controller;

the memory controller reading said memory transfer values stored by the first slave device; and

the memory controller generating addresses to the memory to perform the memory transfer according to said first format based on said memory transfer values;

a second slave device storing a plurality of memory transfer values to identify a transfer of data according to a second format, wherein said second format is different than said first format;

the second slave device generating a request to the memory controller;

the memory controller reading said memory transfer values stored by the second slave device; and

the memory controller generating addresses to the memory to perform the memory transfer according to said second format based on said memory transfer values.

11. The method of claim 10, wherein said first format is a tiled format and said second format is a raster scan format.

12. The method of claim 1, wherein said memory transfer operation comprises transferring an object having an first irregular shape, wherein said object having said first irregular shape is divisible into two or more objects having geometric shapes, wherein said two or more objects having geometric shapes are capable of memory transfers according to a geometric progression, the method further comprising:

the slave device storing a plurality of memory transfer values to identify transfers for each of said two or more objects having geometric shapes, the slave device generating requests to the memory controller for each of said two or more objects having geometric shapes;

the memory controller reading said memory transfer values stored by the slave device for each of said requests; and

the memory controller generating addresses to the memory to perform memory transfers for each of said two or more objects having geometric shapes based on said memory transfer values.

13. A frame memory interface system which accommodates different frame store architectures, comprising:

a memory for storing data;

a memory controller coupled to the memory which controls accesses to the memory;

one or more slave devices coupled to the memory controller, wherein each of said one or more slave devices includes one or more registers for storing a plurality of memory transfer values, wherein said plurality of memory transfer values includes a number of bytes value indicating a number of bytes to be read/written in a row, a skip bytes value indicating a number of bytes to be skipped in a row, and a number of rows value indicating a number of rows to be read/written during the memory transfer, wherein each of said one or more slave devices is configured to program said memory transfer values into said one or more registers according to a desired memory transfer, wherein each of said one or more slave devices is further configured to generate a memory transfer request to said memory controller;

wherein the memory controller is configured to read said memory transfer values from said one or more registers in response to receiving a request from one of said slave devices, and wherein said memory controller is further configured to generate addresses to the memory to transfer data to/from the memory based on said memory transfer values.

14. The frame memory interface system of claim 13, wherein the memory controller is configured to set up an address generation process based on said memory transfer values in response to reading said memory transfer values stored by the slave device;

wherein the memory controller generates addresses to the memory to perform the memory transfer based on said address generation process.

15. The frame memory interface system of claim 13, wherein said one or more registers in each of said slave devices further stores a start address value indicating a page address and offset within the page of the memory where the memory transfer is to begin.

16. The frame memory interface system of claim 13,

wherein each of said one or more slave devices further includes storage buffers where data is read/written from/to said memory;

wherein said one or more registers in each of said slave devices further stores a local start address value indicating a start address for said buffers in said slave device where said data is to be read/written.

17. The frame memory interface system of claim 13, wherein said memory transfer operation comprises transferring an object having a non-rectangular shape, the method further comprising:

wherein said one or more registers in each of said slave devices further stores a left offset value and a right offset value, wherein said left offset value indicates a number of bytes to the left of a start address point and wherein said right offset value indicates a number of bytes to the right of the start address point; and

wherein said one or more registers in each of said slave devices further stores a left increment/decrement value and a right increment/decrement value, wherein said left increment/decrement value indicates an increasing/decreasing progression for a left side of the object, and wherein said right increment/decrement value indicates an increasing/decreasing progression for a right side of the object;

wherein said memory controller generating addresses to the memory to perform the memory transfer using said left and right offset values and said left increment/decrement and right increment/decrement values to generate said addresses to transfer said object having said non-rectangular shape.

18. The frame memory interface system of claim 13, wherein said memory controller further includes arbitration logic for arbitrating among requests from said one or more slave devices.

19. The frame memory interface system of claim 13, wherein said one or more slave devices are capable of performing memory transfers according to a plurality of different frame storage formats;

and

wherein said memory is capable of storing data according to said plurality of different frame storage formats.

20. The frame memory interface system of claim 19, wherein said plurality of different frame storage formats includes a tiled format for storing video data as a plurality of rows of macroblocks and a raster scan format for storing video data in a scan line format.

21. The frame memory interface system of claim 20, wherein said plurality of different frame storage formats further includes a skewed tile format for storing video data as a plurality of rows of macroblocks, wherein macroblocks on neighboring rows are skewed relative to each other.

22. The frame memory interface system of claim 19, wherein said one or more slave devices includes:

a first slave device for performing memory transfers according to a first format, wherein said first slave device stores a plurality of memory transfer values to identify a transfer of data according to said first format;

a second slave device for performing memory transfers according to a second format, wherein said second slave device stores a plurality of memory transfer values to identify a transfer of data according to said second format.

23. The frame memory interface system of claim 22, wherein said first format is a tiled format and said second format is a raster scan format.

24. The frame memory interface system of claim 22, wherein said first slave device comprises reconstruction logic for performing frame reconstruction of temporally compressed video frame data;

and

wherein said second slave device comprises display logic for displaying a frame of video data.

25. The frame memory interface system of claim 24, wherein the temporally compressed video frame data comprises one or more motion vectors which point to a reference block stored in the memory;

wherein the reconstruction logic analyzes said one or more motion vectors and retrieves one or more reference blocks from the memory in response to said one or more motion vectors.

26. The frame memory interface system of claim 13,

wherein the memory stores reference frame data used in frame reconstruction of temporally compressed video frame data;

wherein a first slave device of said one or more slave devices comprises reconstruction logic for performing frame reconstruction of temporally compressed video frame data;

wherein the temporally compressed video frame data comprises one or more motion vectors which point to a reference block stored in the memory;

wherein the reconstruction logic analyzes said one or more motion vectors and retrieves one or more reference blocks from the memory in response to said one or more motion vectors.

wherein said memory stores a reference block in at least first and second pages, wherein said first page stores a first reference block portion and said second page stores a second reference block portion;

wherein the first slave device programs said registers to access the entire first reference block portion of said reference block from said first page, and the first slave device programs said registers to access the entire second reference block portion of said reference block from said second page.

27. The frame memory interface system of claim 13, wherein said memory transfer operation comprises transfer of an object having an first irregular shape, wherein said object having said first irregular shape is divisible into two or more objects having geometric shapes, wherein said two or more objects having geometric shapes are capable of memory transfers according to a geometric progression;

wherein the slave device is configured to store a plurality of memory transfer values to identify transfers for each of said two or more objects having geometric shapes, wherein the slave device is configured to generate requests to the memory controller for each of said two or more objects having geometric shapes;

wherein the memory controller is configured to read said memory transfer values stored by the slave device for each of said requests; and

wherein the memory controller is configured to generate addresses to the memory to perform memory transfers for each of said two or more objects having geometric shapes based on said memory transfer values.