Apparatus for converting and scaling non-interlaced VGA signal to interlaced TV signal

• US 5,912,711 A
• Filed: 05/09/1997
• Issued: 06/15/1999
• Est. Priority Date: 05/07/1997
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC), Lock II, LLC.
• Original Assignee: Umax Data Systems Incorporated
• Inventors: Cheng, Wen-Chin, Ho, Ching-Hung, Lin, Lie-Der, Lee, Ju-Hao
• Primary Examiner(s): Faile, Andrew I.
• Assistant Examiner(s): BERHE, ALEXANDER B
• Application Number:
  US08/853,689
• Time in Patent Office: 767 Days
• Field of Search: 348/446, 348/581, 348/445, 348/441
• US Class Current: 348/446
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

An apparatus for converting and scaling non-interlaced VGA signal to interlaced TV signal suitable to be displayed on a TV video screen is disclosed. The apparatus includes an analog to digital converter, a vertical scaling down device, a vertical scaling up device, a horizontal scaling down device, a horizontal scaling up device, a memory unit, a memory controller, and a digital to analog converter. The apparatus is capable of scaling the non-interlaced VGA signal to interlaced TV signal with any desired scaling size both in horizontal direction and in vertical direction to meet the requirement of displaying operation of the TV screen.

Claims

1. An apparatus for converting non-interlaced VGA scan line signal of a VGA display to an interlaced TV signal and scaling the VGA signal to a desired TV output signal, the apparatus comprising:

analog to digital converting means for receiving and converting an analog RGB current signal of the VGA scan line signal of the VGA display into digital VGA input data;

vertical scaling down means for scaling down the digital VGA input data in a vertical direction to a VGA input signal from the analog to digital converting means by discarding a number of VGA input data corresponding to specific VGA display scan lines in accordance with a scaling down factor;

a memory unit for storing the reduced VGA input signal from the vertical scaling down means;

vertical scaling up means for scaling up the reduced VGA input signal stored in the memory unit in vertical direction to a TV output data by repeating specifically numbered VGA input signals in accordance with a scaling up factor;

digital to analog converting means for converting the TV output data from the vertical scaling up means to TV scan line signals to be displayed on the TV display;

horizontal scaling down means for scaling down the digital VGA input data in horizontal direction by generating VGA clock signals to the analog to digital converting means and adjusting the pulse width of the VGA clock signals to scale down the VGA input data in the horizontal direction; and

horizontal scaling up means for scaling up the reduced VGA input signal stored in the memory unit in horizontal direction by generating TV clock signals to the digital to analog converting and scaling the pulse width of the TV clock signals to scale up the TV output data in horizontal direction.

2. The apparatus as claimed in claim 1, wherein the horizontal scaling down means comprises a phase-locked loop and a VGA timing clock generator, the VGA timing clock generator comprising means to generate a VGA horizontal reference signal to the phase-locked loop, the phase-locked loop being arranged to receive the VGA horizontal reference signal of the VGA timing clock generator and the VGA scan line signals from the VGA display and then generate a synchronous clock signal serving as a sampling signal for the analog to digital converting means.

3. The apparatus as claimed in claim 1, wherein the horizontal scaling up means comprises a phase-locked loop, an OR gate, and a TV timing clock generator, the TV timing clock generator comprising means to supply a first TV horizontal reference signal to the phase-locked loop, the phase-locked loop being arranged to receive the first TV horizontal reference signal of the TV timing clock generator and the TV scan line signals from the TV display and then generate a synchronous clock signal serving as a sampling signal for the digital to analog converting means, the TV timing clock generator further generating a second TV horizontal reference signal as an auxiliary signal, the OR gate being arranged to receive the first TV horizontal reference signal and the second TV horizontal reference signal and then generate a control signal to the vertical scaling up means in order to meet the interlaced display control of the TV display.