Time expansion of pulse width modulation sequences by clock dropping

• US 5,912,712 A
• Filed: 05/11/1998
• Issued: 06/15/1999
• Est. Priority Date: 05/14/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Doherty, Donald B.
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US09/076,335
• Time in Patent Office: 400 Days
• Field of Search: 363/41, 363/42, 348/295, 348/302, 348/439, 348/471, 348/472
• US Class Current: 348/471
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

A method for expanding pulse width modulation sequences that control a display system to adapt to varying video frame times. A minimal amount of extra circuitry (10) is provided that regulates a sequencer (26). After calculating the appropriate expansion factor needed to stretch a base sequence, the system control circuit (22) sends that information to the circuitry (10). The circuitry (10) includes a counter (14) that repetitively counts down a number of clock cycles and causes the clock to drop a cycle. This dropping of clock cycles causes the sequence time to be expanded, as it takes the system longer to reach the necessary number of clock cycles that determine a sequence. Several base pulse width modulation sequences could be stored in memory, each of which can be used for a range of frame times, eliminating the need for one sequence for every possible variation in the frame time.

Claims

1. A method for controlling PWM sequence times in a display system, comprising the steps of:

a) setting said PWM sequence time in said system to be substantially equal to a predetermined number of clock cycles of a sequencer clock;

b) expanding said PWM sequence time by causing said sequencer clock to drop counts, thereby delaying said sequencer clock reaching said predetermined number of clock cycles, resulting in an expanded PWM sequence time; and

c) selecting one of a series of base pulse width modulation sequences, wherein said selection of said one sequence is based upon a display frame time.

2. The method as claimed in claim 1, wherein a counter set with a predetermined drop count determines how often said sequencer clock drops counts.

3. The method as claimed in claim 2, wherein said counter is a down counter.

4. The method as claimed in claim 2, wherein said counter is an up counter.

5. The method as claimed in claim 1, wherein each said sequence has a range of frame times for which it can be used.

6. A circuit operable to cause a sequencer clock in a display system to drop counts, comprising:

a) a register for receiving a drop count, a drop enable signal and a clock signal from a system control circuit;

b) a counter operable to receive said drop count and repetitively count said drop count clock periods wherein said counter sends a signal upon reaching the end of each counting cycle; and

c) a logic circuit operable to receive said drop enable signal and said signal indicating that said counter has reached the end of said counting cycle, upon which reception said logic circuit causes said sequencer clock to drop a count, thereby expanding a sequence time for said display system.

7. The method as claimed in claim 6, wherein said counter is an down counter.

8. The method as claimed in claim 6, wherein said counter is an up counter.

9. The method as claimed in claim 6, wherein said logic circuit further comprises an AND gate and an OR gate.

10. The method as claimed in claim 6 wherein said register is a flip/flop.

11. A method for performing system control of a PWM system with clock dropping, comprising:

a) receiving a frame period signal;

b) determining a frame period from said frame period signal;

c) selecting a base PWM sequence based upon said frame period;

d) providing said base PWM sequence to a PWM sequencer;

e) determining a number of drop counts dependent upon a difference between said base sequence and said frame period; and

f) sending said number of drop counts to a clock dropping circuit along with clock dropping control signals, thereby causing said clock dropping circuit to expand said base sequence appropriately for said frame period.

12. The method as claimed in claim 11, wherein said frame period signal is used to measure said frame period.

13. The method as claimed in claim 11, wherein said frame period signal is a command indicating the frame period.

14. The method as claimed in claim 11, wherein said drop count is determined by calculation.

15. The method as claimed in claim 11, wherein said drop count is determined by finding an appropriate drop count in a look up table.