Method and apparatus for recovering from correctable ECC errors

• US 5,912,906 A
• Filed: 06/23/1997
• Issued: 06/15/1999
• Est. Priority Date: 06/23/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Lauterbach, Gary, Wu, Chang-Hong
• Primary Examiner(s): Grant, William
• Assistant Examiner(s): Marc, McDieunel, Marc, McDieunel
• Application Number:
  US08/880,369
• Time in Patent Office: 722 Days
• Field of Search: 371/40.11, 371/40.14, 371/10.2, 371/37.01, 371/5.1, 370/458, 395/182.5, 395/182.14, 395/185.07, 395/290, 395/800.3, 395/894, 395/182.15, 365/185.21, 365/185.22, 365/229, 375/287, 375/262
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories

Abstract

On-chip delivery of data from an on-chip or off-chip cache is separated into two buses. A fast fill bus provides data to latency critical caches without ECC error detection and correction. A slow fill bus provides the data to latency insensitive caches with ECC error detection and correction. Because the latency critical caches receive the data without error detection, they receive the data at least one clock cycle before the latency insensitive caches, thereby enhancing performance if there is no ECC error. If an ECC error is detected, a software trap is executed which flushes the external cache and the latency sensitive caches that received the data before the trap was generated. If the error is correctable, ECC circuitry corrects the error and rewrites the corrected data back to the external cache. If the error is not correctable, the data is read from main memory to the external cache.

Claims

1. An integrated system comprising:

a first memory cache;

a second memory cache;

a first bus for providing data to said first cache from a third memory cache in response to an instruction;

a second bus for providing said data to said second cache from said third cache in response to said instruction; and

a first ECC circuit, coupled to said second bus, wherein said first ECC circuit checks for errors in said data on said second bus;

wherein said data is provided to said first cache without being checked for errors, such that said data is provided to said first cache at least one clock cycle before said data is provided to said second cache.

2. The integrated system of claim 1, wherein said data from said third cache includes a data field with an ECC bit field appended thereto, and wherein said first ECC circuit checks for errors in said data field and said ECC bit field.

3. The integrated system of claim 1, further comprising:

a trap generator coupled to said first ECC circuit, wherein if said first ECC circuit detects an error in said data, said trap generator generates a trap that causes at least a portion of said first cache to be flushed.

4. The integrated system of claim 3, wherein said data is stored to a first portion of said third cache from a memory, and wherein said generated trap further causes said first portion of said third cache to be flushed.

5. The integrated system of claim 3, wherein said trap further causes said instruction to be restarted if an error is detected by said first ECC circuit.

6. The integrated system of claim 1, wherein said first ECC circuit corrects said data if a correctable error is detected.

7. The integrated system of claim 1, wherein said third cache comprises a SRAM.

8. The integrated system of claim 1, wherein said first cache is one of an instruction cache and a data cache, and wherein said second cache is one of a write cache and a prefetch cache.

9. An integrated system comprising:

a first memory cache on a chip;

a second memory cache on said chip;

a third memory cache, wherein data is stored in said third cache from a memory external to said chip;

a first bus for providing said data to said first cache from said third cache;

a second bus for providing said data to said second cache from said third cache; and

a first ECC circuit, coupled to said second bus, wherein said first ECC circuit checks for errors in said data on said second bus;

wherein said data is provided to said first cache without being checked for errors, such that said data is provided to said first cache at least one clock cycle before said data is provided to said second cache.

10. The integrated chip of claim 9, wherein said third cache comprises a SRAM, and wherein said external memory comprises a DRAM.

11. A method of providing data to a first cache and a second cache in an integrated system from a third cache, the method comprising the steps of:

a) providing data to the first cache from the third cache over a first bus in response to an instruction;

b) providing said data to a first ECC circuit from the third cache over a second bus in response to said instruction;

c) checking said data for errors in said first ECC circuit; and

thereafter

d) providing said data to the second cache from said first ECC circuit over said second bus, such that said data is provided to said first cache at least one clock cycle before said data is provided to said second cache.

12. The method of claim 11, wherein said data from said third cache includes a data field with an ECC bit field appended thereto, wherein said checking step c) includes the step of checking for errors in said data field together with said ECC bit field.

13. The method of claim 11, further including the step of storing said data to a first portion of said third cache from a memory prior to said step a) of providing to said first cache, and wherein said step c) of checking said data includes the step of generating a trap if said first ECC circuit detects an error.

14. The method of claim 13, wherein said step of generating a trap includes the step of flushing said first portion of said third cache and at least a second portion of said first cache.

15. The method of claim 13, wherein said step of generating a trap includes the step of flushing at least a second portion of said first cache.

16. The method of claim 13, further comprising the step of restarting said instruction if said first ECC circuit detects an error.

17. The method of claim 13, wherein said step of generating a trap includes the steps of:

restoring said data to said first portion of said third cache from said memory; and

thereafter

repeating steps a) through d).

18. The method of claim 11, wherein said third cache comprises a SRAM.

19. The method of claim 11, wherein said first external cache is one of an instruction cache and a data cache, and wherein said second cache is one of a write cache and a prefetch cache.

20. The method of claim 11, wherein said step c) of checking includes the step of correcting said data if said first ECC circuit detects a correctable error.