Programmable PCI interrupt routing mechanism

• US 5,913,045 A
• Filed: 12/20/1995
• Issued: 06/15/1999
• Est. Priority Date: 12/20/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Tetrick, Scott, Young, Bruce, Gillespie, Byron
• Primary Examiner(s): Auve, Glenn A.
• Application Number:
  US08/576,452
• Time in Patent Office: 1,273 Days
• Field of Search: 395/306, 395/309, 395/308, 395/733, 395/734, 395/739, 395/735
• US Class Current: 710/311
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

An element of a multi-functional device that integrates a high performance processor into a PCI to PCI bus bridge (P2P). The invention is part of a design that consolidates a high performance processor (the local processor) and other processing elements into a single system which utilizes a local memory. Four PCI interrupt inputs are provided which can be routed to either local processor interrupt inputs or to PCI Interrupt output pins. In this manner, a server designer is able to connect the PCI interrupts directly to the local processor without any jumpers to provide configuration. Additionally, by providing software which would execute on the local processor, the local processor system can intercept the PCI interrupts and process the low level interrupts to create an intelligent I/O subsystem. A simple multiplexor is used to direct the PCI interrupts inputs to the local processor or directs the PCI interrupt inputs directly to the PCI interrupt outputs. The PCI interrupt inputs would be interrupts from PCI devices connected to the secondary PCI bus or PCI add-in cards connected to the secondary PCI bus. The PCI outputs would go directly to an interrupt controller which supports the host processor interrupt structure. This PCI interrupt output mechanism supports the ability to have the local processor intercept the PCI interrupts, determine if the local processor should process the interrupt or forward the interrupt upstream to the host.

Claims

1. An integrated circuit for coupling a first external bus to a second external bus comprising:

a) bus bridge means for allowing transactions to be passed between said first and second external buses;

b) local processor means coupled to said bus bridge means for processing transactions received from external sources and transactions input to said first bus and said second bus;

c) interrupt controller means for routing interrupts generated by devices internal to said integrated circuit and devices external to said integrated circuit such that a plurality of interrupts generated by each of said internal and external devices is consolidated into a single interrupt selectively routed to one of said local processor means and interrupt pins associated with said first external bus.

2. The integrated circuit defined by claim 1 wherein said interrupt controller means comprises:

a) a plurality of multiplexors, each having as its input an interrupt signal, each of said multiplexors for selectively routing its corresponding input to one of said local processor and a set of interrupt output pins;

b) a plurality of latches, each for latching a predetermined set of interrupt signals for input to a corresponding interrupt input of said local processor;

wherein operation of said local processor determines which of a plurality of interrupt sources generated an interrupt currently stored in a corresponding one of said plurality of latches.

3. The integrated circuit defined by claim 2 wherein a first set of said plurality of interrupt sources is DMA Channel 0 Interrupt Pending, DMA Channel 1 Interrupt Pending, DMA Channel 2 Interrupt Pending, DMA Channel 3 Interrupt Pending and XINT6#.

4. The integrated circuit defined by claim 3 wherein a second set of said plurality of interrupt sources is I² C Bus Interface Unit Interrupt Pending, APIC Bus Interface Unit Interrupt Pending, Doorbell Interrupt Pending, Primary Address Translation Unit/Start BIST Interrupt Pending and XINT7#.

5. The integrated circuit defined by claim 4 wherein a third set of said plurality of interrupt sources is Primary PCI Bridge Interface Error, Secondary PCI Bridge Interface Error, Primary Address Translation Unit Error, Secondary Address Translation Unit Error, Local Processor Error, DMA Channel 0 Error, DMA Channel 1 Error, DMA Channel 2 Error, Non-Maskable Interrupt#.

6. The integrated circuit defined by claim 1 wherein said bus bridge means comprises:

a) a primary PCI interface;

b) a secondary PCI interface;

c) a plurality of posting buffers coupled between said primary PCI interface and said secondary PCI interface for handling data flowing between said primary PCI interface and said secondary PCI interface.

7. The integrated circuit defined by claim 1 wherein said local processor means comprises a microprocessor.

8. A system including at least one host processor coupled to a primary PCI bus and at least one peripheral device coupled to a secondary PCI bus, said system comprising the following in a single integrated circuit:

a) a first internal bus coupled to said primary PCI bus;

b) a second internal bus coupled to said secondary PCI bus;

c) bus bridge means having a first bus interface coupled to said first internal bus and a second bus interface coupled to said second internal bus, said bus bridge means for allowing transactions to be passed between said primary PCI bus and said secondary PCI bus;

d) local processor means coupled to said bus bridge means for processing transactions received from external sources and transactions input to said first bus interface and said second bus interface;

e) interrupt controller means for routing interrupts generated by devices internal to said integrated circuit and devices external to said integrated circuit such that a plurality of interrupts generated by each of said internal and external devices is consolidated into a single interrupt selectively routed to one of said local processor means and interrupt pins associated with said first external bus for processing by said host processor.

9. The system defined by claim 8 wherein said interrupt controller means comprises:

a) a plurality of multiplexors, each having as its input an interrupt signal, each of said multiplexors for selectively routing its corresponding input to one of said local processor and a set of interrupt output pins;

b) a plurality of latches, each for latching a predetermined set of interrupt signals for input to a corresponding interrupt input of said local processor;

wherein operation of said local processor determines which of a plurality of interrupt sources generated an interrupt currently stored in a corresponding one of said plurality of latches.

10. The system defined by claim 8 wherein said bus bridge means comprises:

a) a primary PCI interface;

b) a secondary PCI interface;

c) a plurality of posting buffers coupled between said primary PCI interface and said secondary PCI interface for handling data flowing between said primary PCI interface and said secondary PCI interface.

11. The system defined by claim 8 wherein said local processor means comprises a microprocessor.