Method of manufacturing an insulated gate field effect semiconductor device having an offset region and/or lightly doped region

• US 5,913,112 A
• Filed: 03/11/1994
• Issued: 06/15/1999
• Est. Priority Date: 03/06/1991
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko, Yamazaki, Shunpei, Zhang, Hongyong
• Primary Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/209,063
• Time in Patent Office: 1,922 Days
• Field of Search: 257/66, 257/351, 257/408, 257/410, 437/40, 437/44, 437/21, 437/907, 437/908, 437/913, 437/197, 437/201, 437/909, 437/917, 437/170, 437/983, 437/101, 148/DIG. 53, 148/DIG. 117, 438/149, 438/151, 438/153, 438/154, 438/164, 438/165
• US Class Current: 438/165
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

An LDD structure is manufactured to have a desired aspect ratio of the height to the width of a gate electrode. The gate electrode is first deposited on a semiconductor substrate followed by ion implantation with the gate electrode as a mask to form a pair of impurity regions. The gate electrode is then anodic oxidized to form an oxide film enclosing the electrode. With the oxide film as a mask, highly doped regions are formed by ion implantation in order to define lightly doped regions between the highly doped regions and the channel region located therebetween.

Claims

1. A method of manufacturing a plurality of insulated gate field effect semiconductor device comprising the steps of:

forming at least first and second semiconductor islands on an insulating surface;

forming a gate insulating layer on said first and second semiconductor islands;

forming at least first and second gate electrodes over said first and second semiconductor islands, respectively, with said gate insulating layer interposed therebetween;

introducing a first and a second impurity into said first and second semiconductor islands, respectively, with said first and second gate electrodes as masks;

oxidizing the external surface of said first and second gate electrodes which is formed over said first and second semiconductor islands in order to form an oxide layer thereon,

wherein said oxidizing step is carried out in such a manner that the oxide layer of the first gate electrode formed over said first semiconductor island is thicker than the oxide layer of the second gate electrode formed over said second semiconductor island.

2. The method of claim 1 wherein first and second gate electrodes are subjected to an anodic oxidation in said oxidizing step, said anodic oxidation being extended to a longer period on the first gate electrode formed over said first semiconductor island on the second gate electrode formed over said second semiconductor island.

3. The method of claim 1 wherein said oxidizing step is carried out by anodic oxidation.

4. The method of claim 1 wherein said first and second gate electrodes comprise a metal or alloy thereof, said metal selected from the group consisting of titanium, aluminum, tantalum and chromium.

5. The method of claim 1 wherein said oxidizing step is conducted by a plasma oxidation.