Insulated gate thyristor

• US 5,914,503 A
• Filed: 02/13/1997
• Issued: 06/22/1999
• Est. Priority Date: 02/13/1996
• Status: Expired due to Fees

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Iwamuro, Noriyuki, Harada, Yuichi
• Primary Examiner(s): Brown, Peter Toby
• Assistant Examiner(s): DUONG, HUNG V
• Application Number:
  US08/798,743
• Time in Patent Office: 859 Days
• Field of Search: 257/133-136, 257/139, 257/137, 257/138, 257/329, 257/330
• US Class Current: 257/133
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect

Abstract

An insulated gate thyristor is provided in which an inversion layer is created beneath a gate electrode to which a voltage is applied. An emitter region of a first conductivity type is biased to the same potential as a first main electrode via a MOSFET channel, and a thyristor portion consisting of the emitter region, a second base region of a second conductivity type, a base layer of the first conductivity type and an emitter layer of the second conductivity type is turned on. As electrons are injected uniformly from the entire emitter region, the insulated gate thyristor quickly shifts to the thyristor mode, and the on-voltage of the insulated gate thyristor of the invention is lowered. The insulated gate thyristor of the invention does not require a hole current that flows through the second base region of a convention EST in the Z-direction. In turning off, the pn junction recovers quickly without causing current localization, and the breakdown withstand capability if improved.

Claims

1. An insulated gate thyristor comprising:

a highly resistive base layer of a first conductivity type;

a first base region of a second conductivity type, said first base region being selectively formed in the surface portion on a first side of said base layer;

a second base region of said second conductivity type, said second base region being selectively formed in the surface portion on said first side of said base layer;

said first and second base regions being spaced from each other;

a source region of said first conductivity type, said source region being selectively formed in the surface portion of said first base region;

an emitter region of said first conductivity type, said emitter region being selectively formed in the surface portion of said second base region;

a first insulation film on an extended portion of said base layer extended between said first and second base regions, an extended portion of said first base region extended between said source region and said extended portion of said base layer and an extended portion of said second base region extended between said emitter region and said extended portion of said base layer;

a gate electrode on said first insulation film;

a first main electrode commonly contacting with said extended portion of said first base region and said source region;

an emitter layer of said second conductivity type, said emitter layer being on a second side of said base layer;

a second main electrode contacting with said emitter layer;

a second insulation film covering the entire surface of said second base region; and

a resistor on said emitter region, said resistor being connected to said first main electrode.

2. The insulated gate thyristor according to claim 1, wherein said first and second base regions are shaped with stripes facing opposite to each other.

3. The insulated gate thyristor according to claim 1, wherein at least one of said first base region, said second base region, said emitter region and said source region is formed in a shape selected from the group consisting of a polygon, circle and ellipsoid.

4. The insulated gate thyristor according to claim 1, wherein said first base region is around said second base region.

5. The insulated gate thyristor according to claim 1, wherein said first base region is around said second base region, said gate electrode is annular around said second insulation film on said second base region, and said first main electrode is spaced from said second base region by said gate electrode and said second insulation film.

6. The insulated gate thyristor according to claim 1, wherein a plurality of said first base region is around said second base region.

7. The insulated gate thyristor according to claim 6, further comprising base regions of said second conductivity type, wherein said source region of said first conductivity type is not formed.

8. The insulated gate thyristor according to claim 7, wherein said gate electrode is wider on said first base regions, wherein said source region is formed, than on said base regions, wherein said source region is not formed.

9. The insulated gate thyristor according to claim 6, wherein the portion of said source region'"'"'s surface near to said second base region is covered with said second insulation film, and said first main electrode contacts with the portion of said source region'"'"'s surface far from said second base region.

10. The insulated gate thyristor according to claim 1, wherein a plurality of said first base regions is around said second base region, said gate electrode is annular around said second insulation film on said second base region, and said first main electrode is spaced from said second base region by said gate electrode and said second insulation film.

11. The insulated gate thyristor according to claim 10, further comprising base regions of said second conductivity type, wherein said source region of said first conductivity type is not formed.

12. The insulated gate thyristor according to claim 11, wherein said gate electrode is wider on said first base regions, wherein said source region is formed, than on said base regions, wherein said source region is not formed.

13. The insulated gate thyristor according to claim 10, wherein said annular gate electrode comprises a cut-out portion, through which adjacent pair of said plurality of first base region, adjacent source regions in said adjacent pair of first base region and adjacent first main electrodes on said adjacent pair of first base region are connected respectively to each other.

14. The insulated gate thyristor according to claim 13, wherein a first surface portion of one of said adjacent source regions, said first surface portion facing opposite to one of said pairing second base regions, is covered with said second insulation film, and said first main electrode contacts with a second surface portion of said one of said adjacent source regions, said second surface portion facing opposite to the other one of said pairing second base regions.

15. The insulated gate thyristor according to claim 1, wherein the contact portion of said first main electrode with said first base region and said source region is shaped with a shape selected from the group consisting of a polygon, circle and ellipsoid.

16. The insulated gate thyristor according to claim 1, further comprising lifetime killers, said lifetime killers being localized.

17. The insulated gate thyristor according to claim 16, further comprising a heavily doped thin layer of said second conductivity type, said heavily doped thin layer being in the surface portion of said emitter layer.

18. A method of manufacturing the insulated gate thyristor of claim 17, the method comprising the step of forming said heavily doped thin layer of said second conductivity type in the surface portion of said emitter layer by helium ion implantation.

19. The insulated gate thyristor according to claim 1, wherein at least a portion of said source region below the edge of said gate electrode is divided into a plurality of regions.

20. The insulated gate thyristor according to claim 1, wherein said gate electrode is wider between two of said source regions than between said source region and said emitter region.

21. The insulated gate thyristor according to claim 1, further comprising an auxiliary region of said first conductivity type in the surface portion of said base layer beneath said first insulation film, said auxiliary region being doped more heavily than said base layer.

22. The insulated gate thyristor according to claim 1, wherein said second base region is diffused more deeply than said first base region, and said emitter region is diffused more deeply than said source region.

23. The insulated gate thyristor according to claim 1, further comprising a buffer layer of said first conductivity type, said buffer layer being between said base layer and said emitter layer and doped more heavily than said base layer.

24. An insulated gate thyristor comprising:

a highly resistive base layer of a first conductivity type;

a first base region of a second conductivity type, said first base region being selectively formed in the surface portion on a first side of said base layer;

a second base region of said second conductivity type, said second base region being selectively formed in the surface portion on said first side of said base layer;

said first and second base regions being spaced from each other;

a source region of said first conductivity type, said source region being selectively formed in the surface portion of said first base region;

an emitter region of said first conductivity type, said emitter region being in the surface portion of said second base region;

a trench between said first and second base regions, said trench being dug more deeply than said first and second base regions;

a first insulation film covering the inner surface of said trench;

a gate electrode in said trench with said first insulation film interposed between said gate electrode and said trench;

a first main electrode commonly contacting with an extended portion of said first base region and said source region, said extended portion being extended beside said source region;

an emitter layer of said second conductivity type, said emitter layer being on a second side of said base layer;

a second main electrode contacting with said emitter layer; and

a second insulation film covering the entire surface of said second base region;

a resistor on said emitter region, said resistor being connected to said first main electrode.

25. The insulated gate thyristor according to claim 24, wherein said first and second base regions are shaped with stripes facing opposite to each other.

26. The insulated gate thyristor according to claim 24, wherein at least one of said first base region, said second base region, said emitter region and said source region is formed in a shape selected from the group consisting of a polygon, circle and ellipsoid.

27. The insulated gate thyristor according to claim 24, wherein said first base region is around said second base region.

28. The insulated gate thyristor according to claim 24, wherein a plurality of said first base region is around said second base region.

29. The insulated gate thyristor according to claim 28, further comprising base regions of said second conductivity type, wherein said source region of said first conductivity type is not formed.

30. The insulated gate thyristor according to claim 29, wherein said gate electrode is wider on said first base regions, wherein said source region is formed, than on said base regions, wherein said source region is not formed.

31. The insulated gate thyristor according to claim 28, wherein the portion of said source region'"'"'s surface near to said second base region is covered with said second insulation film, and said first main electrode contacts with the portion of said source region'"'"'s surface far from said second base region.

32. The insulated gate thyristor according to claim 24, wherein the contact portion of said first main electrode with said first base region and said source region is shaped with a shape selected from the group consisting of a polygon, circle and ellipsoid.

33. The insulated gate thyristor according to claim 24, wherein at least a portion of said source region below the edge of said gate electrode is divided into a plurality of regions.

34. The insulated gate thyristor according to claim 24, wherein said gate electrode is wider between two of said source regions than between said source region and said emitter region.

35. The insulated gate thyristor according to claim 24, further comprising an auxiliary region of said first conductivity type in the surface portion of said base layer beneath said first insulation film, said auxiliary region being doped more heavily than said base layer.

36. The insulated gate thyristor according to claim 24, further comprising lifetime killers, said lifetime killers being localized.

37. The insulated gate thyristor according to claim 36, further comprising a heavily doped thin layer of said second conductivity type, said heavily doped thin layer being in the surface portion of said emitter layer.

38. A method of manufacturing the insulated gate thyristor of claim 37, the method comprising the step of forming said heavily doped thin layer of said second conductivity type in the surface portion of said emitter layer by helium ion implantation.

39. The insulated gate thyristor according to claim 24, wherein said second base region is diffused more deeply than said first base region, and said emitter region is diffused more deeply than said source region.

40. The insulated gate thyristor according to claim 24, further comprising a buffer layer of said first conductivity type, said buffer layer being between said base layer and said emitter layer and doped more heavily than said base layer.