DRAM applications using vertical MISFET devices

• US 5,914,504 A
• Filed: 06/17/1996
• Issued: 06/22/1999
• Est. Priority Date: 06/16/1995
• Status: Expired due to Term

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: IMEC International
• Inventors: Augusto, Carlos Jorge Ramiro Proenca
• Primary Examiner(s): CRANE, SARA W
• Assistant Examiner(s): CRANE, SARA W
• Application Number:
  US08/664,874
• Time in Patent Office: 1,100 Days
• Field of Search: 257/192, 257/301-306, 257/195, 257/200, 257/201
• US Class Current: 257/192
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

The present invention relates to RAM circuits comprising memory cells and logic circuitry wherein each of the memory cells comprise at least one Vertical MISFET device comprising a stack of several layers a source layer, a channel layer, a drain layer and a capacitor on the top of the stack of several layers of the Vertical MISFET device.

Claims

1. A RAM circuit comprising memory cells and logic circuitry, each of said memory cells comprising at least one Vertical MISFET transistor comprising a stack of multiple layers comprising:

a source layer having a first orientation;

a drain layer also having said first orientation;

a channel layer disposed between said source layer and said drain layer, said channel layer also having said first orientation, wherein a semiconductor heterojunction is formed between said source layer and said channel layer; and

a capacitor on the top of said stack.

2. The RAM circuit of claim 1, wherein said channel layer is undoped or lightly doped and said source layer has an undoped or lightly doped region near the source layer/channel layer interface.

3. The RAM circuit of claim 2 wherein the Vertical MISFET transistor is a Vertical Heterojunction MISFET transistor.

4. The RAM circuit of claim 2 further comprising a gate which at least partially overlaps said source, said channel, and said drain layers, said gate being separated by an insulating layer from said source, said channel, and said drain layers.

5. The RAM circuit of claim 4, wherein said gate has a second orientation, said second orientation being at an angle of about 90 degrees with respect to said first orientation.

6. The RAM circuit of claim 5, wherein the logic circuitry is selected from the group consisting of planar transistors and Vertical MISFET transistors.

7. The RAM circuit of claim 6, wherein the logic circuitry additionally comprises one or more Vertical Heterojunction MISFET transistors.

8. A RAM circuit comprising memory cells and logic circuitry, each of said memory cells comprising at least two of the Vertical MISFET transistors of claim 5 on top of each other with a capacitor therebetween.

9. The RAM circuit of claim 8, wherein the two Vertical MISFET transistors are complementary, wherein the bottom transistor is selected from the group consisting of PMOS and NMOS transistors and the top transistor is selected from the group consisting of NMOS and PMOS transistors.

10. The RAM circuit of claim 8, wherein the logic circuitry is selected from the group consisting of planar transistors and Vertical MISFET transistors.

11. The RAM circuit of claim 10, wherein said logic circuitry comprises one or more Vertical Heterojunction MISFET transistors.