Circuit and method for a folded bit line memory using trench plate capacitor cells with body bias contacts

• US 5,914,511 A
• Filed: 10/06/1997
• Issued: 06/22/1999
• Est. Priority Date: 10/06/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): HUGHES JR, WILLIAM G
• Application Number:
  US08/944,312
• Time in Patent Office: 624 Days
• Field of Search: 257/296, 257/301, 257/302, 257/304, 438/239, 438/242, 438/243
• US Class Current: 257/302
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. A body contact is coupled to the body region of the access transistor that provides a body bias to the access transistor. The access transistor further includes a gate coupled to a word line disposed adjacent to the body region. A passing word line is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Claims

1. A memory cell for a memory array in a folded bit line configuration, the memory cell comprising:

an access transistor formed in a pillar of single crystal semiconductor material, the access transistor having first and second source/drain regions and a body region that are vertically aligned;

a body contact coupled to the body region of the access transistor that provides a body bias to the access transistor;

the access transistor further including a gate coupled to a word line disposed adjacent to the body region;

a passing word line separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell; and

a trench capacitor, wherein the trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

2. The memory cell of claim 1, wherein the second plate of the trench capacitor surrounds the second source/drain region.

3. The memory cell of claim 1, wherein the body contact couples to a body region of an adjacent access transistor.

4. The memory cell of claim 2, wherein the body contact is coupled to the second plate of the trench capacitor.

5. A memory device, comprising:

an array of memory cells, each memory cell including a vertical access transistor formed of a single crystalline semiconductor pillar that extends outwardly from a substrate with body and first and second source/drain regions, a gate disposed adjacent to a side of the pillar adjacent to the body region and a trench capacitor wherein a first plate of the trench capacitor is integral with the first source/drain region and a second plate of the trench capacitor is disposed adjacent to the first plate;

a number of bit lines that are each selectively coupled to a number of the memory cells at the second source/drain region of the access transistor so as to form columns of memory cells in a folded bit line configuration;

a number of word lines disposed substantially orthogonal to the bit lines in trenches between rows of the memory cells, wherein each trench includes two word lines, each word line coupled to gates of alternate access transistors on opposite sides of the trench; and

a number of body contacts disposed between adjacent access transistors in a row of memory cells.

6. The memory device of claim 5, wherein the pillars are disposed on an oxide layer.

7. The memory device of claim 5, wherein a surface area of the memory cell is 4F², where F is a minimum feature size.

8. The memory device of claim 5, wherein the second plate of the trench capacitor surrounds the second source/drain region of the access transistor.

9. The memory device of claim 5, wherein the second plate of the trench capacitor is maintained at approximately ground potential.

10. The memory device of claim 5, wherein the number of body contacts are coupled to a second plate that is common to all of the trench capacitors.

11. The memory device of claim 5, wherein the number of body contacts are coupled between body regions of adjacent access transistors.

12. The memory device of claim 5, wherein the word lines are sub-lithographic.

13. A memory array comprising:

a number of memory cells forming an array with a number of rows and columns, each memory cell including an access transistor having body and first and second source/drain regions formed vertically, outwardly from a substrate and a gate disposed adjacent to a side of the transistor, the second source/drain region including an upper semiconductor surface;

a number of first isolation trenches separating adjacent rows of memory cells;

first and second word lines disposed in each of the first isolation trenches and coupled to alternate gates on opposite sides of the trench;

a number of second isolation trenches, each substantially orthogonal to the first isolation trenches and interposed between adjacent memory cells; and

a number of body contacts disposed in the second isolation trenches that interconnect body regions of adjacent access transistors.

14. The memory array of claim 13, wherein the gates of the access transistors are each formed integral with one of the word lines.

15. The memory array of claim 13, wherein the pillars are disposed on a layer of insulator material.

16. The memory array of claim 13, wherein a surface area of the memory cell is 4F², where F is a minimum feature size.

17. The memory array of claim 13, wherein the trench capacitors share a common second plate that surrounds the second source/drain region of each access transistor.

18. The memory array of claim 17, wherein the body contacts are coupled to the second plate of the trench capacitor.

19. The memory array of claim 13, wherein the body contacts are coupled to a decoder that provides a body bias to the body regions of the access transistors.