Systems and methods for memory control

• US 5,914,543 A
• Filed: 06/07/1995
• Issued: 06/22/1999
• Est. Priority Date: 06/11/1991
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Scherpenberg, Francis A., Mumper, Eric W., Rea, John W., Lee, Robert D.
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): LOCKETT, KIMBERLY R
• Application Number:
  US08/476,410
• Time in Patent Office: 1,476 Days
• Field of Search: 324/426, 324/771, 320/1, 320/5, 320/2, 320/3, 320/15, 320/13, 364/273, 364/DIG. 1, 364/273.1, 364/DIG. 2, 307/64, 307/65, 307/66, 395/180, 395/182.12
• US Class Current: 307/126
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A memory controller for supplying backup battery power when a main power supply voltage drops together with programmable plus power fail write protection. The controller includes supravoltage induced sleep mode operation, MOS switching between backup batteries during backup operation based on battery voltage levels and discharge circuitry for battery disposal.

Claims

1. A system for providing power to at least one memory and for controlling the writing to said memory, comprising:

(a) power supply node;

(b) means for connecting a first voltage source to said power supply node; and

(c) switching circuitry electrically coupled to said power supply node to switch a first circuit from a first mode to a second mode, during a time period when a voltage at said power supply node is outside of the normal operating voltage range by a predetermined percentage,

wherein said first mode is a normal operating state which allows both power to be supplied to said memory and allows writing to said memory when power at said power supply node is within normal tolerances and which supplies power from a backup power source to said memory but inhibits writing to said memory when said power at said supply node is below normal tolerance, and said second mode is a sleep state in which no power is supplied to said memory;

and further wherein said backup power source employs a means to connect two independent backup batteries and wherein a selection from the backup batteries is made by selecting the backup battery having a higher voltage and further wherein the selection can change based upon the discharge of the so selected backup battery.

2. The system of claim 1, wherein said out of normal operating range signal is applied to said power supply node for a first time period.

4. The system as recited in claim 1, wherein said out of tolerance voltage is at least ten percent out of tolerance.

3. A system to discharge a first battery and a second battery, comprising:

(a) a first node of said first battery;

(b) a second node of said second battery;

(c) a battery kill node;

(d) first switching circuitry to selectively electrically couple said first node of said first battery to ground, said first switching circuitry electrically coupled to said battery kill node, so that a signal on said battery kill node causes said first switching circuitry to couple said first node of said first battery to ground; and

(e) second switching circuitry to selectively electrically couple said second node of said second battery to ground, said second switching circuitry electrically coupled to said battery kill node, so that said signal on said battery kill node causes said second switching circuitry to couple said second node of said second battery to ground.