Switching device with power FET and short-circuit detection

• US 5,914,545 A
• Filed: 05/09/1997
• Issued: 06/22/1999
• Est. Priority Date: 05/11/1996
• Status: Expired due to Fees

• Current Assignee: Temic Telefunken Microelectronic GmbH (Continental AG)
• Original Assignee: Temic Telefunken Microelectronic GmbH (Continental AG)
• Inventors: Pollersbeck, Werner
• Primary Examiner(s): PALADINI, ALBERT WILLIAM
• Application Number:
  US08/853,709
• Time in Patent Office: 774 Days
• Field of Search: 307/131, 307/125, 361/100, 361/93, 361/90, 361/88, 361/86, 361/87, 340/650
• US Class Current: 307/131
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches

Abstract

A circuit arrangement protects an FET power switch against damage from short circuits that may occur in the load connected between the drain terminal and an operating voltage source of the FET. The protection is achieved by the cooperation between a shunt resistor (3) connected between ground and the source terminal (S) of the FET and a gate voltage limiter (7) connected to the gate terminal of the FET. This cooperation limits the short circuit current through the FET until a short circuit detector (DT) provides a control signal that switches the FET off.

Claims

1. A circuit arrangement for protecting against an overload an FET power switch (1) having a drain terminal (D), a source terminal (S), and a gate terminal (G), comprising a load (5) connected to said drain terminal (D) and to an operating voltage source (U_B), a short circuit detector (DT) having an input connected to said source terminal (S), a microcontroller (9A) for controlling said FET power switch (1), said short circuit detector (DT) having an output (INT) connected to a control input of said microcontroller (9A) for supplying a control signal representing a short circuit to said control input of said microcontroller, a series resistor (9) connecting a control output of said microcontroller to said gate terminal (G), a gate terminal voltage limiter diode (7) connected to said gate terminal (G) and to a constant clamping voltage, and a shunt resistor (3) connected between said source terminal and ground for cooperation with said gate terminal voltage limiter diode (7) in limiting a short circuit current flowing through said FET power switch at least until said FET power switch (1) is switched off by said control signal in response to a short circuit.

2. The circuit arrangement of claim 1, wherein said microcontroller is a digital microcontroller.

3. The circuit arrangement of claim 1, wherein said constant clamping voltage has the same polarity as a voltage of said control signal when said FET power switch is in its fully conductive state.

4. The circuit arrangement of claim 1, wherein said clamping diode is connected with its anode terminal to said gate terminal and with its cathode terminal to said constant clamping voltage.

5. The circuit arrangement of claim 1, wherein said clamping diode is a zener diode.

6. The circuit arrangement of claim 1, wherein said shunt resistor (3) is part of said short circuit detector (DT), said short circuit detector further comprising a voltage drop evaluating circuit (15) connected to said source terminal (S) and to said shunt resistor (3) for generating said control signal in response to an abnormal voltage drop across said shunt resistor (3).

7. The circuit arrangement of claim 6, wherein said constant clamping voltage and said shunt resistor (3) are so dimensioned that, in response to a short circuit across said load, a short circuit current flowing through the FET power switch is limited by the voltage drop across said shunt resistor to a value that avoids short circuit damage at least until said FET power switch is switched off by said control signal.

8. The circuit arrangement of claim 6, wherein said voltage drop evaluating circuit (15) comprises an operational amplifier (15) having an inverting input, a non-inverting input, and said output (INT) a first resistor (17) connecting said inverting input to said source terminal (S) and to said shunt resistor (3), a second resistor (25) connecting said non-inverting input to a voltage (e.g. 0.5 V), a third resistor (19) connecting said non-inverting input to said output (INT), and a fourth resistor (21) connecting said output (INT) to a voltage (e.g. 5 V).

9. The circuit arrangement of claim 1, wherein said constant clamping voltage of said gate terminal voltage limiter diode (7) and said shunt resistor (3) are so dimensioned that, in response to a short-circuit in said load, the short-circuit current flowing through said FET power switch (1) is limited by a change in source voltage caused by the voltage drop across said shunt resistor (3), to a short-circuit current value that avoids damage to said FET power switch.

10. The circuit arrangernent of claim 9, wherein said constant clamping voltage of said gate terminal voltage limiter diode (7) corresponds to the effective gate voltage of said FET power switch (1) plus a threshold voltage of said gate terminal voltage limiter diode (7).