Method and apparatus for buffering full-motion video for display on a video monitor

• US 5,914,711 A
• Filed: 04/29/1996
• Issued: 06/22/1999
• Est. Priority Date: 04/29/1996
• Status: Expired due to Term

• Current Assignee: Gateway Incorporated (Acer, Inc.)
• Original Assignee: Gateway 2000, Inc. (Acer, Inc.)
• Inventors: Farwell, Randall S., Mangerson, Mark M.
• Primary Examiner(s): Brier, Jeffery
• Assistant Examiner(s): Kovalick, Vincent E.
• Application Number:
  US08/638,769
• Time in Patent Office: 1,149 Days
• Field of Search: 345/185, 345/189, 345/201, 345/507, 345/508, 345/203, 348/441, 348/448, 348/422, 395/118, 395/501, 395/507-509, 395/512
• US Class Current: 345/547
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2310/0229 De-interlacing
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

Triple-buffering video memory in a computer graphics controller improves the quality of full-motion video converted for display on a computer monitor. Buffer size, organization, and access cycles prevent converted data representing a new video frame from overwriting a buffer in memory that contains converted data representing a video frame currently being displayed. The access cycles also ensure all data representing a video frame is displayed. The video memory is partitioned into three logical buffers to hold the converted data, the buffers are arranged in a logical ring sequence for read and write access, and the data in a buffer is repeatedly read until the next buffer in the sequence is full of data and ready to be read. In addition, the buffering is adaptable to different resolutions as the size of the buffers is determined by the value of the resolution each time the video conversion is initiated.

Claims

1. A method for improving the quality of full-motion video displayed on a video monitor controlled by display processing circuitry that converts frames in a video stream into a corresponding series of display blocks and stores the display blocks in a memory for display on the monitor, the method comprising the steps of:

partitioning the memory into three logical buffers, wherein each buffer is sized to hold a display block;

writing the display block first in the series into a first buffer; and

performing a storage-and-retrieval loop until the display block last in the series has been completely read, the storage-and-retrieval loop comprising the steps of;

repeatedly reading the entire display block from the first buffer while writing the next display block in the series into a second buffer until the second buffer is full;

repeatedly reading the display block from the second buffer while writing the next display block in the series into a third buffer until the third buffer is full; and

repeatedly reading the display block from the third buffer while writing the next display block in the series into the first buffer until the first buffer is full.

2. The method of claim 1, further comprising the step of:

partitioning each logical buffer into first and second equal segments, wherein a first field of the display block representing odd picture lines in an interlaced frame is written into the first segment, and a second field of the display block representing even picture lines in the interlaced frame is written into the second segment to store the display block in memory as interlaced.

3. The method of claim 2, wherein reading a display block results in first the first segment and then the second segment being output such that the display block is output as an interlaced video frame.

4. The method of claim 2, wherein each buffer is further partitioned into a plurality of display lines and reading a display block alternates between reading one of the plurality of display lines in the first segment and one of the plurality of display lines in the second segment to output the display block as a non-interlaced video frame.

5. The method of claim 1, wherein each logical buffer is partitioned into alternating first and second pluralities of display lines, and writing a display block writes to each one of the first plurality of display lines and then to each one of the second plurality of display lines to store the display block in memory as non-interlaced.

6. The method of claim 5, wherein reading a display block alternates between reading one of the first plurality of display lines and one of the second plurality of display lines to output the display block as a non-interlaced video frame.

7. The method of claim 5, wherein reading a display block reads each one of the first plurality of display lines and then each one of the second plurality of display lines to output the display block as an interlaced video frame.

8. The method of claim 1, wherein a display block read from a buffer before at least one buffer is full is not output to the monitor.

9. The method of claim 1, wherein a read of a display block from a buffer is not performed until at least one buffer is full.

12. A computer-readable medium having computer-executable instructions stored thereon for performing the steps recited in claim 1.

10. A method for improving the quality of full-motion video displayed on a video monitor controlled by display processing circuitry that converts frames in a video stream into a corresponding series of display blocks and stores the display blocks in a memory for display on the monitor, the method comprising the steps of:

partitioning the memory into three logical buffers, wherein each buffer is large enough to hold a display block and the buffers are arranged in a logical ring for access in a pre-determined sequence; and

writing the series of display blocks into successive buffers while continuously displaying on the monitor an entire display block read from a buffer until the next display block in the series is completely written to the next buffer in the sequence so that only complete frames are displayed on the monitor.

11. A system for improving the quality of full-motion video displayed on a video monitor comprising:

display processing circuitry for converting frames in a video stream into corresponding series of display blocks for output on the monitor;

memory accessible by the display processing circuitry for temporarily storing the display blocks until output on the monitor;

initialization means in the display processing circuitry for partitioning the memory into three logical buffers each sized to hold a display block and arranging the buffers in a logical ring for access in a pre-determined sequence; and

cyclical accessing means for writing the series of display blocks into successive buffers while continuously reading an entire display block from a buffer until the next display block in the series is completely written to the next buffer in the sequence so that only complete frames are output on the monitor.

13. A computer-readable medium having computer-executable instructions stored thereon for performing the steps of:

partitioning a memory into three logical buffers, wherein each buffer is large enough to hold a display block that corresponds to a frame in a video stream and the buffers are arranged in a logical ring for access in a pre-determines sequence; and

writing a series of display blocks into successive buffers while continuously displaying on a monitor an entire display block read from a buffer until the next display block in the series is completely written to the next buffer in the sequence so that only complete frames of video data are displayed on the monitor and display blocks in the buffers are displayed in the order in which the corresponding frames appear in the video stream.