Index and storage system for data provided in the vertical blanking interval

• US 5,914,719 A
• Filed: 12/03/1996
• Issued: 06/22/1999
• Est. Priority Date: 12/03/1996
• Status: Expired due to Term

• Current Assignee: S3 Graphics Co., Ltd. (HTC Corporation)
• Original Assignee: S3 Inc. (SONICblue Incorporated)
• Inventors: Herz, William S.
• Primary Examiner(s): Nguyen, Phu K.
• Assistant Examiner(s): Vo, Cliff N.
• Application Number:
  US08/753,923
• Time in Patent Office: 931 Days
• Field of Search: 345/418, 345/419, 345/420, 345/423, 348/617
• US Class Current: 345/418
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: H04N 7/0885 for the transmission of subtitles

Abstract

A graphics display system processes text data in a video signal, preferably in the vertical blanking interval, and allows a user to selectively display the text data in real time, search the text data, or obtain a transcript of the data. A digitizer and decoder circuit extracts the text data from a video signal and adds an identifier to the text data. A graphics user interface accelerator stores the text data. Concurrent with adding the identifier and the storage of the text data, the digitizer and decoder circuit adds an identifier to the video and audio data, and the graphics user interface accelerator stores the video and audio data. The identifier added to the video and audio data links such data to the associated text data. In response to a user search request, a host processor scans the stored text data for text data that matches a user selected input, and retrieves the text data matching the user selected input. In response to a user command, the host processor retrieves the video and audio data having an identifier matching the identifier of the retrieved text data. The graphics user interface accelerator displays the video data and plays the retrieved audio data. In response to another user command, the host processor provides the retrieved text data to an external device for printing.

Claims

1. A method for processing text data in a video signal, the method comprising the steps of:

(a) extracting the text data from a video signal;

(b) adding an identifier to the text data;

(c) storing the text data;

concurrent with steps (b) and (c),

(d) adding an identifier to the video and audio data linking the video and audio data to the text data; and

(e) storing the video and audio data.

2. The method of claim 1 further comprising the steps of:

scanning the stored text data for text data that matches a user selected input; and

retrieving the text data matching the user selected input.

3. The method of claim 2 further comprising the step of:

retrieving the video and audio data having an identifier matching the identifier of the retrieved text data.

4. The method of claim 3 further comprising the step of displaying the retrieved video data and playing the retrieved audio data.

5. The method of claim 4 further comprising the step of displaying the text data concurrently with the retrieved video data.

6. The method of claim 2 further comprising the step of:

printing the retrieved text data.

7. The method of claim 1 wherein the identifier is indicative of the elapsed time of the text data relative to a reference time.

8. The method of claim 1 wherein the text data is stored independently of the video data to provide unaltered text data independent of scaling of the text data.

9. The method of claim 1 further comprising the step of displaying the text data in real time.

10. A system for processing and displaying text data in a video signal, the system comprising:

a decoder circuit for extracting the text data from a video signal and for adding an identifier to the text data and for adding the identifier to the video and audio data in the video signal, concurrently with the adding of the identifier to the text data so that the identifier links the video and audio data to the text data;

an accelerator, coupled to the decoder, for receiving the text data and the video and audio data from the decoder circuit and for outputting the text data along with the video and audio data;

a memory, coupled to the accelerator, for storing the text data and the video and audio data; and

a display, coupled to the accelerator, for displaying the retrieved video data and playing the retrieved audio data.

11. The system of claim 10 further comprising:

a host processor having an input for receiving a user selected input and coupled to the memory for scanning the stored text data for text data that matches the user selected input, and for retrieving the text data matching the user selected input.

12. The system of claim 11 wherein the host processor retrieves from the memory the video and audio data having an identifier matching the identifier of the retrieved text data.

13. The system of claim 11 wherein the host processor provides the retrieved text data to an external device for printing.

14. The system of claim 10 wherein the identifier is indicative of the elapsed time of the text data relative to a reference time.

15. The system of claim 10 wherein the decoder circuit and the memory are included in a computer.

16. The system of claim 10 further comprising:

a digital-to-analog converter, coupled to the display, for transforming the text data and the video data into a format for viewing on the display.

17. The system of claim 10 wherein the decoder circuit comprises:

a close caption decoder for extracting text data from the video signal;

a close caption processor coupled to the close caption decoder, for buffering the text data; and

an output processor, coupled to the close caption processor, for generating a formatted video data.

18. The system of claim 17 wherein the formatted video data generated by the output processor is in a YUV format.

19. The system of claim 17 further comprising:

a video signal processor, coupled to the output processor, for receiving the video signal and providing luminance and chrominance components of the video signal.

20. A decoder circuit comprising:

a close caption decoder stage for extracting text data from a video signal;

a close caption processor, coupled to the close caption decoder stage, for buffering the text data; and

an output processor, coupled to the close caption processor, for generating a formatted video data,

wherein the decoder circuit adds an identifier to the video signal so that the video is linked with the text data.

21. The decoder circuit of claim 20 wherein the close caption processor transmits the text data in a first field and, alternatively, transmits the text data in a second field.

22. The decoder circuit of claim 20 further comprising:

a video signal processor, coupled to the output processor, for receiving the video signal and providing luminance and chrominance components of the video signal.

23. The decoder circuit of claim 22 further comprising:

an automatic gain control (AGC) and clamping circuit, coupled to the close caption decoder stage and the video signal processor, for receiving the video signal.

24. The decoder circuit of claim 20 wherein the formatted video data generated by the output processor is in a YUV format.

25. The decoder circuit of claim 20 wherein the close caption decoder stage comprises:

a comparator circuit having an input terminal for receiving the video signal and an output terminal;

a phase lock loop circuit having an input terminal and an output terminal;

a line detector and timer circuit having an input terminal for receiving the video signal, a first output terminal, and a second output terminal;

an input-enabling AND gate having an output terminal coupled to the input terminal of the phase lock loop circuit, a first input terminal for receiving the video signal, and a second input terminal coupled to the first output terminal of the line detector and timer circuit;

a signal-enabling AND gate having a first input terminal coupled to the output terminal of the phase lock loop circuit, a second input terminal coupled to the second output terminal of the line detector and timer circuit, and an output terminal; and

a shift register having a first input terminal coupled to the output terminal of the comparator circuit, a second input terminal coupled to the output terminal of the signal-enabling AND gate, and an output terminal coupled to the closed captioning processor, the shift register capable of serially shifting the text data and generating the text data in parallel.

26. The decoder circuit of claim 20 wherein the close caption processor comprises:

a first buffer having an input terminal coupled to the close caption decoder and an output terminal;

a second buffer having an input terminal coupled to the close caption decoder and an output terminal;

a multiplexer having an input terminal for receiving text data from the first buffer and the second buffer, the multiplexer having an output terminal for providing the text data to the output processor; and

a state register for indicating the processing of closed caption text by the decoder circuit and for indicating if the closed caption text is contained in an odd field or even field of the video signal.

27. The decoder circuit of claim 20 wherein the output processor comprises:

a format processor coupled to the video signal processor and to the close caption processor, the format processor capable of formatting the text data and the video signal into a formatted video data; and

an output memory, coupled to the format processor, for generating the formatted video data.

28. The decoder circuit of claim 22 wherein the video signal processor comprises:

a luminance processor for receiving the video signal and for providing a luminance component to the video signal; and

a chrominance processor for receiving the video signal and for providing a chrominance component to the modified video signal.