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System and method for invalidating and updating individual GART table entries for accelerated graphics port transaction requests

  • US 5,914,730 A
  • Filed: 09/09/1997
  • Issued: 06/22/1999
  • Est. Priority Date: 09/09/1997
  • Status: Expired due to Term
First Claim
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1. A computer system, comprising:

  • a system processor executing software instructions and generating graphics data;

    a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address;

    the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said system memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage;

    a graphics processor generating video display data from the graphics data and adapted for connection to a video display to display the video display data;

    a first interface logic for connecting said system processor to said system memory;

    a second interface logic for connecting said system processor and said system memory to said graphics processor;

    said second interface logic having a cache memory and a cache entry control register;

    said cache memory having a plurality of storage locations, each of the plurality of storage locations comprising an address portion, an entry portion, an entry update portion and an entry invalidate portion;

    a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of GART table entries comprising an address pointer to a corresponding one of the plurality of pages of graphics data; and

    said second interface logic reading selected ones of the plurality of GART table entries and storing the selected ones in the entry portions of the plurality of storage locations of said cache memory, the storage locations being associated with graphics device addresses asserted by said graphics processor; and

    said cache entry control register adapted to receive information for a graphics device address, an entry update and an entry invalidate from an applications programming interface (API) of the software instructions;

    wherein,if the received information through said cache entry control register causes the entry update portion to be set to a first logic level, said second interface logic will read the plurality of GART entries and update a one of the plurality of storage locations associated with the graphics device address received by said cache entry control register; and

    if the received information through said cache entry control register causes the entry invalidate portion to be set to the first logic level, said second interface logic will invalidate the one of the plurality of storage locations associated with the graphics device address received by said cache entry control register.

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