System and method for invalidating and updating individual GART table entries for accelerated graphics port transaction requests
First Claim
1. A computer system, comprising:
- a system processor executing software instructions and generating graphics data;
a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address;
the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said system memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage;
a graphics processor generating video display data from the graphics data and adapted for connection to a video display to display the video display data;
a first interface logic for connecting said system processor to said system memory;
a second interface logic for connecting said system processor and said system memory to said graphics processor;
said second interface logic having a cache memory and a cache entry control register;
said cache memory having a plurality of storage locations, each of the plurality of storage locations comprising an address portion, an entry portion, an entry update portion and an entry invalidate portion;
a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of GART table entries comprising an address pointer to a corresponding one of the plurality of pages of graphics data; and
said second interface logic reading selected ones of the plurality of GART table entries and storing the selected ones in the entry portions of the plurality of storage locations of said cache memory, the storage locations being associated with graphics device addresses asserted by said graphics processor; and
said cache entry control register adapted to receive information for a graphics device address, an entry update and an entry invalidate from an applications programming interface (API) of the software instructions;
wherein,if the received information through said cache entry control register causes the entry update portion to be set to a first logic level, said second interface logic will read the plurality of GART entries and update a one of the plurality of storage locations associated with the graphics device address received by said cache entry control register; and
if the received information through said cache entry control register causes the entry invalidate portion to be set to the first logic level, said second interface logic will invalidate the one of the plurality of storage locations associated with the graphics device address received by said cache entry control register.
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Accused Products
Abstract
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. A GART cache entry control register is used by an application programming interface, such as a GART miniport driver, to indicate to the core logic chipset that an individual GART table entry in the chipset cache should be invalidated and/or updated. The core logic chipset may then perform the required invalidate and/or update operation on the individual GART table entry without having to flush or otherwise disturb the other still relevant GART table entries stored in the cache.
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Citations
52 Claims
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1. A computer system, comprising:
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a system processor executing software instructions and generating graphics data; a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address; the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said system memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage; a graphics processor generating video display data from the graphics data and adapted for connection to a video display to display the video display data; a first interface logic for connecting said system processor to said system memory; a second interface logic for connecting said system processor and said system memory to said graphics processor; said second interface logic having a cache memory and a cache entry control register; said cache memory having a plurality of storage locations, each of the plurality of storage locations comprising an address portion, an entry portion, an entry update portion and an entry invalidate portion; a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of GART table entries comprising an address pointer to a corresponding one of the plurality of pages of graphics data; and said second interface logic reading selected ones of the plurality of GART table entries and storing the selected ones in the entry portions of the plurality of storage locations of said cache memory, the storage locations being associated with graphics device addresses asserted by said graphics processor; and said cache entry control register adapted to receive information for a graphics device address, an entry update and an entry invalidate from an applications programming interface (API) of the software instructions;
wherein,if the received information through said cache entry control register causes the entry update portion to be set to a first logic level, said second interface logic will read the plurality of GART entries and update a one of the plurality of storage locations associated with the graphics device address received by said cache entry control register; and if the received information through said cache entry control register causes the entry invalidate portion to be set to the first logic level, said second interface logic will invalidate the one of the plurality of storage locations associated with the graphics device address received by said cache entry control register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A computer system having a core logic chipset which connects a central processing unit and random access memory to an accelerated graphics port (AGP) bus, said system comprising:
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a central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chipset connected to the host bus and the random access memory bus; said core logic chipset having a first interface bridge for connecting the host bus to the random access memory bus; said core logic chipset having a second interface bridge for connecting the host bus to an accelerated graphics port (AGP) bus; said core logic chipset having a third interface bridge for connecting the random access memory bus to the AGP bus; said core logic chipset having a cache memory and a cache entry control register; said cache memory having a plurality of storage locations, each of the plurality of storage locations comprising an address portion, an entry portion, an entry update portion and an entry invalidate portion; said core logic chipset using a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of GART table entries comprising an address pointer to a corresponding one of a plurality of pages of graphics data stored in said random access memory; said core logic chipset reading selected ones of the plurality of GART table entries stored in said random access memory and storing the selected ones of the plurality of GART table entries in the entry portions of the plurality of storage locations of said cache memory, each of the entry portions associated with a one of the address portions; and said cache entry control register adapted to receive information for a graphics device address, an entry update and an entry invalidate;
wherein,if the received information through said cache entry control register causes the entry update portion to be set to a first logic level, said core logic chipset will read the plurality of GART entries and update a one of the plurality of storage locations associated with the graphics device address received by said cache entry control register; and if the received information through said cache entry control register causes the entry invalidate portion to be set to the first logic level, said core logic chipset will invalidate the one of the plurality of storage locations associated with the graphics device address received by said cache entry control register. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A method, in a computer system, of updating and invalidating individual selected ones of a plurality of graphics address remapping table (GART table) entries stored in a cache memory, said method comprising the steps of:
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storing a plurality of pages of graphics data in any order in a computer system memory; storing a plurality of entries of a graphics address remapping table (GART table) in the computer system memory, wherein each one of the plurality of GART table entries corresponds to a one of the plurality of pages of graphics data stored in the computer system memory; reading selected ones of the plurality of GART table entries stored in the computer system memory; storing the selected ones read from the computer system memory into a cache memory, wherein the cache memory has a plurality of storage locations, each of the plurality of storage locations comprising a graphics device address portion, an entry portion, an entry update portion and an entry invalidate portion, wherein the selected ones are stored in the entry portions; writing a first logic level to the entry update portion of a one of the plurality of storage locations when an associated one of the selected ones requires updating from the computer system memory; and writing the first logic level to the entry invalidate portion of a one of the plurality of storage locations when an associated one of the selected ones is invalid. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49)
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50. A core logic chipset adapted for connection to a computer central processing unit and random access memory, an accelerated graphics port (AGP) bus and a peripheral component interconnect (PCI) bus, comprising:
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an accelerated graphics port (AGP) request queue; an AGP reply queue; an AGP data and control logic; said AGP data and control logic having an AGP cache entry control register; an AGP cache memory; said AGP cache memory having a plurality of storage locations, each of the plurality of storage locations comprising a graphics device address portion, an entry portion, an entry update portion and an entry invalidate portion; an AGP arbiter; a host to peripheral component interconnect (PCI) bridge; a PCI to PCI bridge; a memory interface and control logic adapted for connecting to a computer system random access memory; and a host bus interface adapted for connecting to a computer system host bus having at least one central processing unit connected thereto;
wherein,said AGP request and reply queues are connected to said memory interface and control logic; said AGP data and control logic is connected to said memory and interface control logic; said AGP data and control logic is connected to the host bus interface; said host to PCI bus bridge is connected to the host bus interface and is adapted for connection to a PCI bus; said PCI to PCI bridge is connected to said AGP data and control logic, wherein said PCI to PCI bridge transfers PCI information transactions between said Host to PCI bus bridge and said AGP data and control logic; said AGP data and control logic and said AGP arbiter adapted for connection to an AGP bus having an AGP device;
whereinsaid AGP data and control logic is adapted to use a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of GART table entries comprising an address pointer to a one of a plurality of pages of graphics data stored in the computer system random access memory; said AGP data and control logic is adapted to read selected ones of the plurality of GART table entries stored in said random access memory and is adapted to store the selected ones of the plurality of GART table entries in the entry portions of the plurality of storage locations of said cache memory, each of the entry portions associated with a one of the graphics device address portions; and said cache entry control register adapted to receive information for a graphics device address, an entry update and an entry invalidate;
wherein,if the entry update of the received information causes the entry update portion to be set to a first logic level, said AGP data and control logic is adapted to update from the GART table entries stored in said random access memory the one of the plurality of storage locations associated with the graphics device address; and if the entry invalidate of the received information causes the entry invalidate portion to be set to the first logic level, said AGP data and control logic is adapted to invalidate the one of the plurality of storage locations associated with the graphics device address. - View Dependent Claims (51, 52)
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Specification