Switched network hub on a chip

• US 5,914,955 A
• Filed: 03/28/1995
• Issued: 06/22/1999
• Est. Priority Date: 10/20/1993
• Status: Expired due to Term

• Current Assignee: LSI Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Desai, Sanjay, Rostoker, Michael D., Daane, John P., Stelliga, D. Tony
• Primary Examiner(s): HSU, ALPUS
• Application Number:
  US08/412,861
• Time in Patent Office: 1,547 Days
• Field of Search: 370/357, 370/360, 370/395, 370/396, 370/400-408, 370/410, 370/419-421, 370/428, 370/465-467, 370/471, 370/474, 370/522, 364/514 R, 364/514 A, 364/514 C, 395/285, 395/309, 395/311, 395/500, 395/800, 395/200.79, 395/200.8
• US Class Current: 370/395.5
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 12/5602 Bandwidth control in ATM Networks, e.g. leaky bucket
• CPC Class Codes: H04L 2012/5613 Bus (including DQDB)
• CPC Class Codes: H04L 2012/5614 User Network Interface
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5628 Testing
• CPC Class Codes: H04L 2012/5632 Bandwidth allocation
• CPC Class Codes: H04L 2012/5635 Backpressure, e.g. for ABR
• CPC Class Codes: H04L 2012/5636 Monitoring or policing, e.g. compliance with allocated rate, corrective actions
• CPC Class Codes: H04L 2012/5637 Leaky Buckets
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5647 Cell loss
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5653 using the ATM adaptation layer [AAL]
• CPC Class Codes: H04L 2012/5664 Support of Video, e.g. MPEG
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/0817 by checking functioning
• CPC Class Codes: H04L 43/0852 : Delays
• CPC Class Codes: H04L 43/10 : Active monitoring, e.g. heartbeat, ping or trace-route
• CPC Class Codes: H04L 43/106 : using time related information in packets, e.g. by adding timestamps
• CPC Class Codes: H04L 45/745 : Address table lookup; Address filtering
• CPC Class Codes: H04L 47/10 : Flow control; Congestion control
• CPC Class Codes: H04L 47/11 : Identifying congestion
• CPC Class Codes: H04L 47/263 : Rate modification at the source after receiving feedback
• CPC Class Codes: H04L 47/43 : Assembling or disassembling of packets, e.g. segmentation and reassembly [SAR]
• CPC Class Codes: H04L 49/109 : Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/20 : Support for services
• CPC Class Codes: H04L 49/206 : Real Time traffic
• CPC Class Codes: H04L 49/25 : Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/30 : Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 : Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3081 : ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/355 : Application aware switches, e.g. for HTTP
• CPC Class Codes: H04L 49/501 : Overload detection
• CPC Class Codes: H04L 49/505 : Corrective measures
• CPC Class Codes: H04L 49/555 : Error detection
• CPC Class Codes: H04L 49/557 : Error correction, e.g. fault recovery or fault tolerance
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9057 : Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9063 : Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9078 : using an external memory or storage device
• CPC Class Codes: H04L 49/9094 : Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04N 19/00 : Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 19/70 : characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 21/2381 : Adapting the multiplex stream to a specific network, e.g. an Internet Protocol [IP] network transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/4143 : embedded in a Personal Computer [PC]
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/437 : Interfacing the upstream path of the transmission network, e.g. for transmitting client requests to a VOD server flow control in data networks H04L47/10; streaming protocols, e.g. RTP or RTCP, H04L65/65; scheduling or organising the servicing of application requests in data packet switching networks H04L67/60
• CPC Class Codes: H04N 21/4381 : Recovering the multiplex stream from a specific network, e.g. recovering MPEG packets from ATM cells transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/4385 : Multiplex stream processing, e.g. multiplex stream decrypting
• CPC Class Codes: H04N 21/4788 : communicating with other users, e.g. chatting arrangements for providing for computer conferences, e.g. chat rooms, to substation in data switching networks H04L12/1813; distributed application using peer-to-peer [P2P] networks H04L67/104
• CPC Class Codes: H04N 21/64 : Addressing network arrangements, protocols or services for addressing or naming H04L61/00; support for multicast or broadcast of one-way stream services H04L65/611
• CPC Class Codes: H04N 21/64307 : ATM
• CPC Class Codes: H04Q 11/0478 : Provisions for broadband connections
• CPC Class Codes: H04Q 2213/13034 : A/D conversion, code compression/expansion
• CPC Class Codes: H04Q 2213/13097 : Numbering, addressing
• CPC Class Codes: H04Q 2213/13141 : Hunting for free outlet, circuit or channel
• CPC Class Codes: H04Q 2213/13174 : Data transmission, file transfer
• CPC Class Codes: H04Q 2213/13204 : Protocols
• CPC Class Codes: H04Q 2213/13216 : Code signals, frame structure
• CPC Class Codes: H04Q 2213/13296 : Packet switching, X.25, frame relay
• CPC Class Codes: H04Q 2213/13322 : Integrated circuits
• CPC Class Codes: H04Q 2213/13332 : Broadband, CATV, dynamic bandwidth allocation
• CPC Class Codes: H04Q 2213/13353 : Routing table, map memory

Abstract

A network adapter formed on a single semiconductor substrate. The network adapter includes a host bus interface circuit adapted to be connected to a host data bus. A buffer memory is connected to the host bus interface circuit and temporarily stores digital information received from the host data bus. The digital information received from the host data bus are reformatted into packets according to a network protocol by a reformatting circuits. A processor and a network interface circuit are connected to the reformatting circuits. The processor controls the reformatting of the digital information. The network interface circuit is adapted to be connected to a digital network employing the network protocol.

Claims

1. An adapter circuit for connection between a parallel cell interface (PCI) bus and an asynchronous transfer mode (ATM) network, comprising:

a PCI controller and FIFOs for data communication with the PCI bus in PCI bus format;

a buffer memory for storing data in PCI and ATM network formats, said buffer memory being connected to the PCI bus controller and FIFOs for receiving data in PCI format therefrom;

a microprocessor for handling conversion of data from ATM format to PCI format, said microprocessor being connected to the PCI controller and FIFOs for transmitting thereto data that has been converted from ATM format to PCI format;

an ATM segmentation and assembly unit for segmenting and assembly of ATM data packets, said ATM segmentation and assembly unit being connected to the buffer memory for transmitting thereto and receiving therefrom data in ATM format;

an ATM transmission convergence unit for interfacing with said ATM network for receiving and transmitting ATM data packets to and from the ATM segmentation and assembly unit; and

a synchronous optical network/synchronous digital hierarchy (SONET/SDH) framer unit for interfacing with the ATM network, said SONET/SDH framer unit being connected to the ATM transmission convergence unit for receiving therefrom and transmitting thereto ATM data packets.

2. The adapter circuit of claim 1, wherein said PCI controller and FIFOs, buffet memory, microprocessor, ATM segmentation and assembly unit, ATM transmissior convergence unit, and SONET/SDH framer unit are formed on a single chip.

3. The adapter circuit of claim 2, wherein said single chip further includes physical-layer dependent (PMD) unit for ATM network line transceiving and clock recovery operations.