Clock skew reduction
First Claim
1. A computer system having a circuit for synchronizing the phase of a first periodic signal in one integrated circuit device with a second periodic signal in another integrated circuit device connected to the one integrated circuit device by a connection that imposes a propagation delay, the system comprising:
- a first integrated circuit device including an integrated circuit output coupled to the connection;
a receiver with an input connected to the connection to receive the second periodic signal delayed by the propagation delay;
circuitry for providing a delay signal representative of the propagation delay; and
a generator connected to the receiver and to the circuitry for providing, the generator to generate the first periodic signal in phase with the second periodic signal based on the first periodic signal and the delay signal.
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Accused Products
Abstract
A computer system has a skew compensation circuit for synchronizing the phase of a first periodic signal in one device with a second periodic signal in a second device connected to the first device by a connection that imposes a propagation delay. The skew compensation circuit has a receiver connected to receive the second periodic signal delayed by the propagation delay and circuitry for providing a delay signal representative of the propagation delay. The skew compensation circuit further includes a generator connected to generate the first periodic signal in phase with the second periodic signal based on the first periodic signal and the delay signal.
41 Citations
58 Claims
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1. A computer system having a circuit for synchronizing the phase of a first periodic signal in one integrated circuit device with a second periodic signal in another integrated circuit device connected to the one integrated circuit device by a connection that imposes a propagation delay, the system comprising:
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a first integrated circuit device including an integrated circuit output coupled to the connection; a receiver with an input connected to the connection to receive the second periodic signal delayed by the propagation delay; circuitry for providing a delay signal representative of the propagation delay; and a generator connected to the receiver and to the circuitry for providing, the generator to generate the first periodic signal in phase with the second periodic signal based on the first periodic signal and the delay signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A computer system comprising:
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a communication link; a source device coupled to the communication link to furnish a source timing signal to the communication link, the source timing signal being subject to a first propagation delay caused by the communication link; a target device connected to receive the source timing signal from the communication link; circuitry coupled to the communication link to send and receive a second signal along the communication link, the second signal with a second propagation delay that has a predetermined relationship to the first propagation delay; and circuitry connected to the target device to provide the source timing signal to the target device with a timing based on the second propagation delay. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for use in a computer system for compensating for propagation delay in a signal passed from a signal source to a signal destination, the method comprising:
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sensing an amount of actual time delay indicative of the propagation delay; and adjusting the phase of the signal as received from the signal source in accordance with the sensed propagation delay. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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28. A circuit for synchronizing the phase of a first periodic signal in one device with a second periodic signal in a second device connected to the first device by a connection that imposes a propagation delay, the circuit comprising:
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a receiver connected to receive the second periodic signal delayed by the propagation delay; circuitry for providing a delay signal representative of the propagation delay; and a generator coupled to the receiver and the circuitry to generate a compensated periodic signal in phase with the first periodic signal based on the second periodic signal and the delay signal. - View Dependent Claims (29, 30, 31, 32, 33, 34)
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35. A circuit for synchronizing the phase of a periodic signal in one device with a second periodic signal in a second device connected to the first device by a periodic signal line that imposes a propagation delay, comprising:
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a receiver coupled to the periodic signal line to receive the second periodic signal delayed by the propagation delay; a conductor for receiving a signal in phase with the first periodic signal and for providing a delay signal representative of the propagation delay; and a phase lock loop coupled to the receiver and to the conductor to generate a compensated periodic signal in phase with the first periodic signal based on the second periodic signal and the delay signal.
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36. A system comprising:
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a first integrated circuit device including a signal output node; a second integrated circuit device including a compensation circuit having a signal input node and a compensated signal output node; and a line coupling the signal output node of the first integrated circuit device to the signal input node of the compensation circuit, the line introducing a propagation delay such that a signal at the signal input node of the compensation circuit will be out of phase with a clock signal at the signal output node of the first integrated circuit device by an amount equal to the propagation delay of the line; wherein the compensation circuit provides a compensated signal at the compensated signal output node, the compensated signal being substantially in-phase with the signal at the signal output node of the first integrated circuit device. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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47. A computer system comprising:
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a CPU; a memory coupled for access by the CPU; a reference clock circuit including a clock signal output, the clock signal output being coupled to the CPU; a compensation circuit having a clock input signal node and a compensated clock signal output node; a line coupling the clock signal output node of the reference clock to the clock signal input node of the compensation circuit, the line introducing a propagation delay such that a clock signal at the clock signal input node of the compensation circuit will be out of phase with a clock signal at the clock signal output node of the reference clock by an amount equal to the propagation delay of the line; and an integrated circuit device with a clock signal input coupled to the compensated clock signal output node of the compensation circuit, the integrated circuit device receiving a compensated clock signal at the clock signal input, the compensated clock signal being substantially in-phase with the clock signal at the clock signal output node of the reference clock circuit. - View Dependent Claims (48, 49, 50)
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51. A circuit comprising:
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a phase lock loop with a first input, a second input, and an output, the first input to receive a periodic signal with a first propagation delay; an averaging circuit with first and second inputs and an output, the first input of the averaging circuit coupled to the output of the phase lock loop, the second input of the averaging circuit coupled to receive a periodic signal with a second propagation delay that has a known relation to the first propagation delay, the output of the averaging circuit coupled to the second input of the phase lock loop. - View Dependent Claims (52, 53)
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54. A system comprising:
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a first integrated circuit including a first integrated circuit output node; a second integrated circuit including a second integrated circuit input node; a conductor including a first node coupled to the first integrated circuit output node and a second node, the conductor introducing a propagation delay to a signal being transmitted from the first node of the conductor to the second node of the conductor; a reference conductor having first and second nodes, the reference conductor introducing a reference propagation delay to a signal being transmitted from the first node of the reference conductor to the second node of the reference conductor, the reference propagation delay being about twice the propagation delay of the conductor; and a compensation circuit disposed physically near to the second integrated circuit, the compensation circuit including a first input node coupled to the first integrated circuit output node, the compensation circuit further including a second input node the first node of the reference conductor, the compensation circuit further including an output node coupled to second integrated circuit input node. - View Dependent Claims (55, 56, 57, 58)
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Specification