Syncronizing a data acquisition device with a host

• US 5,914,991 A
• Filed: 06/30/1997
• Issued: 06/22/1999
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Draeger Medical Systems Incorporated (FPS Vermögensverwaltung GmbH)
• Original Assignee: Siemens Medical Systems, Inc. (Siemens AG)
• Inventors: Sullivan, John F., Gigandet, Scott, Addiss, Robert
• Primary Examiner(s): Vo, Don N.
• Assistant Examiner(s): JIANG, LENNY R
• Application Number:
  US08/884,857
• Time in Patent Office: 722 Days
• Field of Search: 375/355, 375/354
• US Class Current: 375/355
• CPC Class Codes: A61B 5/0002 Remote monitoring of patients using telemetry, e.g. transmission of vital signals via a communication network A61B5/07 takes precedence; transmission systems for measured values G08C; transmission H04B; transmission of digital information H04L; wireless communication networks H04W
• CPC Class Codes: A61B 5/1455 using optical sensors, e.g. spectral photometrical oximeters
• CPC Class Codes: A61B 5/282 Holders for multiple electrodes for introduction into the body A61B5/287
• CPC Class Codes: H03L 7/0993 and a circuit for adding and deleting pulses
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Apparatus for synchronizing a reference clock signal received from a host system with an A/D converter clock signal generated in a data acquisition pod. The pod includes a decoder responsive to communication received from the host for extracting a host reference signal, and a clock signal source for developing an A/D reference clock signal having a frequency that is different from the frequency of the host reference signal. A pulse modifying digital phase-locked loop (PLL) is responsive to the A/D reference clock signal and the host reference signal for developing an A/D clock signal for an A/D converter in which one of its clock periods is periodically modified, thereby locking the rate at which the A/D converter develops samples to the rate at which the host system requests samples. In a preferred embodiment the pod also includes a signal detector for detecting a specified alignment in time of the readiness of the A/D converter to provide a given sample with a host system request for that given sample, and upon such detection, selectively providing an enable signal to the PLL, thereby enabling operation of the PLL and synchronizing the host and pod clock rates, as well as locking in a given alignment the providing to the host of the samples developed by the A/D converter with the host system requests for those samples.

Claims

1. In a data acquisition pod of the type having a signal sampling A/D converter that is coupled to a host system via a data communication link, apparatus for synchronizing a host-derived reference clock signal with a clock signal in the data acquisition pod that operates the A/D converter, so that the A/D converter provides samples to the data communication link at the same rate as the rate at which the host system requests the samples, comprising:

a decoder having an input coupled to the data communication link for extracting from communication received from the host a host reference signal having a host reference frequency;

a clock signal source for developing an A/D reference clock signal having a frequency that is offset a predetermined amount from the frequency of the host reference frequency;

an A/D converter of the oversampling type having an A/D converter clock signal input; and

a pulse modifying digital phase-locked loop (PLL) responsive to the A/D reference clock signal and the host reference signal for developing an A/D clock signal in which one of its clock periods is periodically modified, said A/D reference clock signal being coupled to said A/D converter clock signal input, thereby locking the rate at which the A/D converter develops samples to the rate at which the host system requests samples.

2. Apparatus in accordance with claim 1, wherein said decoder, signal detector and said PLL are formed using an ASIC.

3. Apparatus in accordance with claim 1, wherein the decoder is responsive to a plurality of sample requests from the host system for extracting the host reference frequency.

4. Apparatus in accordance with claim 1, wherein the A/D converter is of the sigma-delta type.

5. Apparatus in accordance with claim 1, wherein the frequency of said A/D reference clock signal is slightly greater than the frequency of said host reference signal, and said pulse modifying PLL is a pulse stealing PLL, developing an A/D clock signal in which one of its clock periods is periodically stretched.

6. Apparatus in accordance with claim 1, wherein said A/D converter develops a sequence of a plurality of samples, and said data acquisition pod further includes:

a signal detector responsive to the host system requests for samples and the readiness of the A/D converter to provide those samples for detecting a specified aligmient in time of a given sample of said sequence of samples with a host system request for that given sample, and upon such detection, selectively providing an enable signal to the PLL, thereby enabling its pulse modifying operation and locking in a given alignment the providing to the communication link of the plurality of samples developed by the A/D converter with the requests by the host system for those samples.

7. Apparatus in accordance with claim 6, wherein said A/D converter comprises a plurality of A/D converters operating in parallel on a respective one of a corresponding plurality of analog input signals, each A/D converter providing an A/D READY signal to said signal detector for indicating its readiness to provide digital samples.

8. Apparatus in accordance with claim 7, wherein said plurality of A/D converters provide said digital samples as a serial data stream.

9. Apparatus in accordance with claim 6, wherein said data acquisition pod includes error checking circuitry responsive to said sample requests from the host system for examining each sample requests on a sample by sample basis, and if any sample request is missing, out of order from a pre-determined sample order, or becomes un-synchronized with the specified sequence that samples are ready to be provided by the A/D converter, removes the enable signal from the PLL so that the time at which the given sample is ready to be provided by the A/D converter is allowed to slip with respect to the time that the host system requests that given sample.

10. Apparatus in accordance with claim 9, wherein said decoder, signal detector, error checking circuitry and PLL are formed using an ASIC.

11. Apparatus in accordance with claim 9, wherein after removing said enable signal, said error checking circuitry remains responsive to said sample requests from the host system for re-detecting the specified alignment in time of the given sample of the sequence of samples with a host system request for that given sample, and includes means responsive to said re-detection for then re-applying said enable signal to said PLL.

12. A method for synchronizing a reference clock signal that operates a host system with a clock signal developed in a data acquisition pod that operates an A/D converter in the pod, so that the A/D converter provides samples to a data communication link connecting the host and pod at the same rate as the rate at which the host system requests the samples, the method comprising:

decoding communications received over the data communication link from the host system for extracting a host reference signal having a host reference frequency;

providing a clock signal source for an A/D reference clock signal having a frequency that is different from the host reference frequency;

developing a sequence of a plurality of digital samples of at least one analog input signal using an oversampling type of A/D converter having an A/D converter clock signal input; and

developing an A/D clock signal that is synchronized with the host reference signal by using a pulse modifying phase-locked loop (PLL) responsive to the A/D reference clock signal and the host reference signal, said PLL causing one of the clock periods of the A/D clock signal to be periodically modified, said A/D reference clock signal being coupled to said A/D converter clock signal input, thereby locking the rate at which the A/D converter develops samples to the rate at which the host system requests samples.

13. The method of claim 12, wherein said decoding step decodes a plurality of sample requests from the host system for extracting the host reference frequency.

14. The method of claim 12, wherein said step of developing a sequence of digital samples uses a sigma delta A/D converter for providing said samples as a serial data stream.

15. The method of claim 12, wherein the frequency of said A/D reference clock signal is slightly greater than the frequency of said host reference signal, and said step of developing an A/D clock signal develops an A/D clock signal in which one of its clock periods is periodically stretched.

16. The method of claim 12, comprising the further step of:

detecting the timing of the host system requests for a sequence of samples and the readiness of the A/D converter to provide those samples, for selectively providing an enable signal to the PLL upon detecting a specified alignment in time of a given sample of sequence of samples with a host system request for that given sample, thereby enabling said PLL pulse modifying operation and locking in a given time alignment the providing to the host of the sequence of samples developed by the A/D converter with the host system requests for those samples.

17. The method of claim 16, wherein said detector step detects an A/D READY signal from a plurality of A/D converters operating in parallel on a respective one of a corresponding plurality of analog input signals, each A/D READY signal indicating its readiness to provide digital samples.

18. The method of claim 12, including the further step of error checking said sample requests from the host system on a sample by sample basis, and if any sample request is missing, out of order from a pre-determined sample order, or becomes un-synchronized with the sequence that samples are ready to be provided by the A/D converter, removes the enable signal from the PLL so that the time at which the given sample is ready to be provided by the A/D converter is allowed to slip with respect to the time that the host system requests that given sample.

19. The method of claim 18, wherein said error checking step, after removing said enable signal, continues to check said sample requests from the host system for re-detecting the specified alignment in time of the given sample of the sequence of samples with a host system request for that given sample, and includes a step for re-applying said enable signal to said PLL upon said re-detection.