Scannable sense amplifier circuit

• US 5,915,084 A
• Filed: 09/26/1997
• Issued: 06/22/1999
• Est. Priority Date: 09/30/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wendell, Dennis L.
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): FOLLANSBEE, JOHN A
• Application Number:
  US08/938,734
• Time in Patent Office: 634 Days
• Field of Search: 371/21.1, 371/22.31, 371/22.36, 371/22.5, 371/70, 365/201, 365/205, 395/183.06, 395/555
• US Class Current: 714/30
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/32 Serial access; Scan testing
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/14 : Word line organisation; Word line lay-out
• CPC Class Codes: H03K 2005/00019 : Variable delay
• CPC Class Codes: H03K 2005/00071 : by adding capacitance as a load
• CPC Class Codes: H03K 3/356156 : with synchronous operation
• CPC Class Codes: H03K 5/13 : Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03L 7/08 : Details of the phase-locked loop
• CPC Class Codes: H03L 7/0995 : the oscillator comprising a ring oscillator

Abstract

A plurality sense amplifiers have first and second internal nodes representing respectively, true and complement values of a latched value. A plurality of transfer circuits are provided with one of the transfer circuits disposed between and coupled to each adjacent pairs of the sense amplifiers. The transfer circuits transfer true and complement values between a previous and a next sense amplifier, thereby providing a scannable sense amplifier.

Claims

1. An apparatus comprising:

a plurality sense amplifiers, each of said sense amplifiers having a first and second internal node representing respectively, true and complement values of a latched value; and

a plurality of transfer circuits, one of said transfer circuits disposed between and coupled to each adjacent pair of said sense amplifiers, said transfer circuits transferring said true and complement values between a previous and a next sense amplifier;

wherein

said sense amplifiers are alternately grouped as even sense amplifiers and odd sense amplifiers and are coupled to respective columns of a memory array and are coupled to form a scan chain via said transfer circuits, each of said odd sense amplifiers being coupled to latch a sensed value on assertion of a first clock signal and each of said even sense amplifiers being coupled to latch a sensed value on assertion of a second clocks signal; and

a first group of said transfer circuits are coupled to a first transfer signal and a second group of said transfer circuits are coupled to a second transfer signal, and wherein said first and second transfer signals are asserted to transfer data from said previous to said next sense amplifier in said scan chain, and said first and second clock signals are asserted to latch said transferred data into respective sense amplifiers.

2. An apparatus as recited in claim 1 wherein each of said transfer circuits is comprised of two NMOS transistors.

3. The apparatus as recited in claim 1 wherein each of said sense amplifiers includes a latching circuit, and wherein each latching circuit is coupled to one of said first and second clock signals.

4. An apparatus as recited in claim 1 wherein each of said sense amplifiers comprises:

a first and second transistor coupled as a cross coupled pair, a first electrode of said first transistor being coupled to a gate electrode of said second transistor, and a first electrode of said second transistor being coupled to a gate electrode of said first transistor and wherein said gate electrodes of said first and second transistors are respectively coupled to first and second bit lines through isolation transistors;

a latch transistor having a gate electrode coupled to one of said first and second clock signals, said latch transistor having a first electrode coupled to second electrodes of said first and second transistors and having a third electrode coupled to ground; and

wherein

each said transfer circuit comprises a first transfer transistor and a second transfer transistor, said first transfer transistor being coupled to said gate electrode of said first transistor on each sense amplifier adjacent to said transfer circuit, and wherein said second transfer transistor is coupled to said gate electrode of said second transistor on each said sense amplifier adjacent to said transfer circuit, and wherein said gate electrodes of said first and second transfer transistors are coupled to one of said first and second transfer signals.

5. The apparatus of claim 4 wherein said cross coupled pair, said latch transistor and said first and second transfer transistors are NMOS transistors.

6. The apparatus as recited in claim 1 wherein said apparatus is one of an SRAM integrated circuit and a DRAM integrated circuit.

7. An apparatus comprising:

a plurality sense amplifiers, each of said sense amplifiers having a first and second internal node representing respectively, true and complement values of a latched value; and

a plurality of transfer circuits, one of said transfer circuits disposed between and coupled to each adjacent pair of said sense amplifiers, said transfer circuits transferring said true and complement values between a previous and a next sense amplifier;

wherein each said sense amplifier comprises;

a latching circuit, each latching circuit being coupled to one of said first and second clock signals;

a first transistor having a first and second electrode, and a first gate electrode, said first electrode being coupled to a supply voltage;

a second transistor having a third and fourth electrode and a second gate electrode, said third electrode being coupled to said supply voltage, said first and second gate electrodes being coupled respectively to first and second bit lines through isolation transistors, said first bit line representing a true value of a value stored said array and said second bit line representing a complement value of said value stored in said array, said second electrode of said first transistor being coupled to said second bit line at a first internal node in said sense amplifier, and said fourth electrode of said second transistor being coupled to said first bit line at a second internal node in said sense amplifier;

a third transistor having a fifth and sixth electrode and a third gate electrode, said fifth electrode being coupled to said first internal node and said third gate electrode being coupled to said second internal node;

a fourth transistor having a seventh and eighth electrodes and a fourth gate electrode, said seventh electrode being coupled to said second internal node and said fourth gate electrode being coupled to said first internal node; and

wherein

said latching circuit comprises a fifth transistor having a ninth and a tenth electrode and a fifth gate electrode, said ninth electrode being coupled to said sixth and eighth electrodes and said tenth electrode being coupled to ground, and wherein said fifth gate electrode is coupled to one of said first and second clock signals.

8. The apparatus as recited in claim 7 wherein each said transfer circuit comprises a sixth and seventh transistor, said sixth transistor having eleventh and twelfth electrodes and a sixth gate electrode, and said seventh transistor having thirteenth and fourteenth electrodes and a seventh gate electrode, said sixth and seventh gate electrodes being coupled to one of said first and second transfer signals, and wherein eleventh and twelfth electrodes are coupled to first internal nodes in adjacent sense amplifiers and wherein said thirteenth and fourteenth electrodes are coupled to said second internal nodes in adjacent sense amplifiers.

9. The apparatus as recited in claim 8 wherein said first and second transistors are PMOS and said fourth through seventh transistors are NMOS.

10. An apparatus comprising:

a plurality of transfer circuits;

a plurality of sense amplifiers coupled to a storage array, each of said sense amplifiers being coupled to a next one of said sense amplifiers via one of said transfer circuits to form a scan chain, each of said sense amplifiers having a latching circuit, and wherein a first group of latching circuits in odd numbered sense amplifiers in said scan chain are coupled to a first clock signal and a second group of latching circuits in even numbered sense amplifiers in said scan chain are coupled to a second clock signal;

a first transfer signal coupled to even numbered transfer circuits; and

a second transfer signal coupled to odd numbered transfer circuits.

11. An apparatus as recited in claim 10, wherein for each internal sense amplifier in said scan chain, said internal sense amplifier being coupled to two transfer circuits, each internal sense amplifier has a first node coupled to a true bit line and a second node coupled to a complement bit line, and wherein each of said first and second nodes are connected to respective nodes of an upstream and downstream transfer circuit.

12. The apparatus as recited in claim 10 wherein said next one of said sense amplifiers is physically adjacent to a previous one of said sense amplifiers with a transfer circuit disposed between said previous and said next one.

13. The apparatus as recited in claim 10 wherein data is transferred in a first direction in said scan chain upon application of a first sequence of said first, second, third and fourth clocks and wherein data is transferred in a second direction in said scan chain upon application of a second sequence of said first, second, third and fourth clocks, thereby providing for bi-directional shifting through said scan chain.

14. A method of scanning a plurality of sense amplifiers of a memory array coupled in a scan chain, said plurality of sense amplifiers including a first group of sense amplifiers and a second group of sense amplifiers, each of said sense amplifiers being coupled to a next one of said sense amplifiers via a respective one of a plurality of transfer circuits, said transfer circuits including a first group and a second group, said method comprising:

asserting a first transfer signal coupled to said first group of transfer circuits to provide a first group of signals respectively held in said first group of sense amplifiers to said second group of sense amplifiers; and

asserting a second sense amplifier clock to store respective ones of said first group of signal values into said second group of sense amplifiers, thereby shifting said first group of signals from said first group of sense amplifiers to said second group of sense amplifiers.

15. The method as recited in claim 14 further comprising:

asserting, prior to assertion of said first transfer signal, a first sense amplifier clock to store said first group of signal values representing logic levels stored in said memory array into said first group of sense amplifiers.

16. The method as recited in claim 14 further comprising:

asserting a second transfer signal coupled to said second group of transfer circuits to provide a second group of signals from said second group of sense amplifiers to said first group of sense amplifiers; and

asserting a first sense amplifier clock to store said second group of signals into said first group of sense amplifiers, thereby shifting said respective signals from said second group of sense amplifiers to said first group of sense amplifiers.

17. The method as recited in claim 14 wherein at least one of said first and second transfer signals and at least one of said first and second sense amplifier clocks are asserted so as to overlap for at least a portion of an active period of respective ones of said transfer signals and said clocks.