Three dimensional structure memory

• US 5,915,167 A
• Filed: 04/04/1997
• Issued: 06/22/1999
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Picardat, Kevin M.
• Assistant Examiner(s): COLLINS, DEVEN M
• Application Number:
  US08/835,190
• Time in Patent Office: 809 Days
• Field of Search: 438/108, 438/107, 438/455
• US Class Current: 438/108
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/81 using a hierarchical redundancy scheme
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage
• CPC Class Codes: G11C 29/848 by adjacent switching
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/29109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/29118 Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/29124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/29166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/29169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A method of forming a random-access memory, comprising the steps of:

fabricating a memory circuit on a first substrate;

fabricating a memory controller circuit on a second substrate;

bonding the first and second substrates to form interconnects between the memory circuit and the memory controller circuit, neither the first substrate alone nor the second substrate alone being sufficient to provide random access data storage, wherein said bonding is thermal diffusion bonding of the first substrate to the second substrate, and the backside of one of said substrates is thinned and then processed to form interconnection that pass through said one of said substrates and to form contacts on the backside of said one of said substrates.

2. The method of claim 1, wherein at least some of said interconnects are fine-grain vertical interconnects having a pitch of less than 100 μ

m.

3. The method of claim 2, comprising the step of further bonding the stacked IC structure and a further substrate.

4. The method of claim 3, wherein said further bonding is thermal diffusion bonding of the stacked IC structure and the further substrate to one another.

5. The method of claim 4, wherein said thermal diffusion bonding uses fine-grain contact patterns having a contact pitch of less than 100 um.

6. The method of claim 5, wherein said fine-grain contact patterns form extensions of the fine-grain vertical interconnects.

7. The method of claim 1, comprising the step of further bonding the stacked IC structure and a further substrate.

8. The method of claim 7, wherein said further bonding is wire bonding of a singulated stacked IC structure and the further substrate.

9. The method of claim 1, wherein at least some of the interconnects arc formed by a planar process.

10. The method of claim 7, wherein said further bonding is thermal diffusion metal bonding of fine-grain vertical interconnect contact pattern of a singulated stacked IC structure and the further stacked IC or conventional circuit IC.

11. The method of claim 7, wherein said further bonding is thermal diffusion metal bonding of an interconnect contact pattern of a singulated stacked IC structure and the further stacked IC or conventional circuit IC.

12. The method of claim 10, wherein the first and second substrates are wire bonded to a third substrate.

13. The method of claim 1, comprising the further steps of:

fabricating at least one additional memory circuit on at least one additional substrate; and

bonding the at least one additional substrate to the stacked IC substrate and forming interconnects between the at least one additional memory circuit and the memory controller circuit, wherein at least some of the interconnects pass through a substrate on which a memory circuit is formed.

14. The method of claim 1, wherein said backside of said one of said substrates is thinned such that a thin device layer remains.

15. The method of claim 14, wherein at least some of said interconnects are fine-grain vertical interconnects having a pitch of less than 100 μ

m.

16. The method of claim 14, wherein said thinned substrates are thinned to less than 50 μ

m in thickness.

17. The method of claim 14, wherein semiconductor portions of the thinned substrates are thinned to a thickness in the range of about 1-8 μ

m.

18. The method of claim 14, wherein said thinning comprises grinding said substrates.

19. The method of claim 18, wherein said substrates are ground subsequent to being bonded.

20. The method of claim 18, wherein said substrates are ground prior to being bonded.

21. The method of claim 13, wherein at least one memory circuit is formed on a reusable substrate, further comprising the stop of separating a layer in which the memory circuit is formed from the reusable substrate.

22. The method of claim 21, wherein the at least one memory circuit is formed of polysilicon transistors.

23. The method of claim 13, wherein mating contact patterns are formed on respective surfaces to be bonded together.

24. The method of claim 23, wherein said mating contact patterns are formed predominantly of metal.

25. The method of claim 24, wherein said metal includes metal selected from a group consisting of:

Al, Sn, Ti, In, Pb, Zn, Ni, Cu, Pt and Au, and alloys thereof.

26. The method of claim 13, wherein said memory circuits and said memory controller circuit are semiconductor circuits, and wherein the memory controller circuit is fabricated using a first semiconductor process technology and the memory circuits are formed using a second distinct semiconductor process technology.

27. The method of claim 26, wherein the first semiconductor process technology employs active semiconductor devices of both a first type and a second complementary type.

28. The method of claim 26, wherein semiconductor devices formed in accordance with the second semiconductor process technology include MOS semiconductor devices, the MOS semiconductor devices all being of a single type.

55. The method of claim 1, comprising the further step of locating within the memory controller sense amplifiers, and coupling the sense amplifiers to data lines of the memory circuit.

56. The method of claim 55, comprising the further step of using the sense amplifiers to discriminate between more than two signal levels, and producing from each sense amplifier a multi-level output signal.

57. The method of claim 1, wherein said memory controller circuit is fabricated using a semiconductor process technology, and said memory circuits are formed using a different process technology.

58. The method of claim 57, wherein said different process technology is selected from a group consisting of:

DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

59. The method of claim 1, wherein surfaces bonded by thermal diffusion bonding include interconnect metallization and non-interconnect metallization;

whereby thermal diffusion bonding simultaneously achieves electrical interconnection through said interconnect metallization and mechanical bonding through said non-interconnect metallization.

60. The method of claim 59 wherein, prior to said thermal diffusion bonding, at least one of the surfaces to be bonded is planarized using chemical/mechanical polishing.

61. The method of claim 60, wherein both of the surfaces to be bonded are planarized using chemical/mechanical polishing.

62. The method of claim 1, wherein said substrates are semiconductor wafers.

63. The method of claim 62 comprising the further step of dicing a resulting stacked wafer into individual stacked ICs.

64. The method of claim 1, wherein said memory controller circuit and said memory circuit are formed using low-stress dielectric.

65. The method of claim 13, comprising the further step of, during backside processing of a final substrate to form part of said random-access memory, forming bond pads on the backside of the final substrate.

68. The method of claim 64, wherein both of the surfaces to be bonded are planarized using chemical/mechanical polishing.

29. A method of bonding together multiple substrates each having integrated circuits formed thereon to form interconnections between the integrated circuits, the method comprising the steps of:

processing a mating surface on each of first and second substrates to achieve substantial planarity of the mating surfaces;

forming mating, fine-grain interconnect patterns on the mating surfaces;

performing fine-grain, planar thermal diffusion bonding of the mating surfaces; and

thinning at least one of said substrates on which said integrated circuits are formed to form a thinned substrate, facilitating formation of said interconnects, and performing backside processing of said thinned substrate.

30. The method of claim 29, wherein said thermal diffusion bonding of the first substrate to the second substrate forms a stacked IC structure.

31. The method of claim 30, wherein at least some of said interconnects are fine-grain vertical interconnects having a pitch of less than 100 μ

m.

32. The method of claim 31, comprising the step of further bonding the stacked IC structure and a further substrate.

33. The method of claim 32, wherein said further bonding is thermal diffusion bonding of the stacked IC structure and the further substrate to one another.

34. The method of claim 33, wherein said thermal diffusion bonding uses fine-grain contact patterns having a contact pitch of less than 100 μ

m.

35. The method of claim 34, wherein said fine-grain contact patterns form extensions of the fine-grain vertical interconnects.

36. The method of claim 29, comprising the step of further bonding the stacked IC structure and a further substrate.

37. The method of claim 36, wherein said further bonding is wire bonding of a singulated stacked IC structure and the further substrate.

38. The method of claim 29, wherein at least some of the interconnects are formed by a planar process.

39. The method of claim 36, wherein said further bonding is thermal diffusion metal bonding of fine-grain vertical interconnect contact pattern of a singulated stacked IC structure and the further stacked IC or conventional circuit IC.

40. The method of claim 36, wherein said further bonding is thermal diffusion metal bonding of an interconnect contact pattern of a singulated stacked IC structure and the further stacked IC or conventional circuit IC.

41. The method of claim 39, wherein the first and second substrates are wire bonded to a third substrate.

42. The method of claim 29, wherein said backside of said one of said substrates is thinned such that a thin device layer remains.

43. The method of claim 42, wherein at least some of said interconnects are fine-grain vertical interconnects having a pitch of less than 100 μ

m.

44. The method of claim 42, wherein said thinned substrates are thinned to less than 50 μ

m in thickness.

45. The method of claim 42, wherein semiconductor portions of the thinned substrates are thinned to a thickness in the range of about 1-8 μ

m.

46. The method of claim 42, wherein said thinning comprises grinding said substrates.

47. The method of claim 46, wherein said substrates are ground subsequent to being bonded.

48. The method of claim 46, wherein said substrates are ground prior to being bonded.

49. The method of claim 41, wherein at least one integrated circuit is formed on a reusable substrate, further comprising the step of separating a layer in which the integrated circuit is formed from the reusable substrate.

50. The method of claim 49, wherein the at least one integrated circuit is formed of polysilicon transistors.

51. The method of claim 41, wherein bonding comprises thermal diffusion bonding.

52. The method of claim 51, wherein mating contact patterns are formed on respective surfaces to be bonded together.

53. The method of claim 52, wherein said mating contact patterns are formed predominantly of metal.

54. The method of claim 53, wherein said metal includes metal selected from a group consisting of:

Al, Sn, Ti, In, Pb, Zn, Ni, Cu, Pt and Au, and alloys thereof.

66. The method of claim 29, wherein surfaces bonded by thermal diffusion bonding include interconnect metallization and non-interconnect metallization;

whereby thermal diffusion bonding simultaneously achieves electrical interconnection through said interconnect metallization and mechanical bonding through said non-interconnect metallization.

67. The method of claim 29, wherein, prior to said thermal diffusion bonding, at least one of the surfaces to be bonded is planarized using chemical/mechanical polishing.

69. The method of claim 29, wherein said substrates are semiconductor wafers.

70. The method of claim 69, comprising the further step of dicing a resulting stacked wafer into individual stacked ICs.

71. The method of claim 29, wherein said integrated circuits are formed using low-stress dielectric.

72. The method of claim 34, comprising the further step of, during backside processing of a final substrate to form part of said random-access memory, forming bond pads on the backside of the final substrate.

73. A method of bonding together multiple substrates each having integrated circuits formed thereon to form interconnections between the integrated circuits, the method comprising the steps of:

preparing on each of the first and second substrates substantially planar mating surfaces having mating contact patterns;

performing thermal diffusion bonding of the mating surfaces; and

thinning at least one of said substrates on which said integrated circuits are formed to form a thinned substrate, facilitating formation of said interconnects, and performing backside processing of said thinned substrate.