Lid wafer bond packaging and micromachining

• US 5,915,168 A
• Filed: 05/06/1998
• Issued: 06/22/1999
• Est. Priority Date: 08/29/1996
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Salatino, Matthew M., Young, William R., Begley, Patrick A.
• Primary Examiner(s): Picardat, Kevin M.
• Assistant Examiner(s): COLLINS, DEVEN M
• Application Number:
  US09/073,776
• Time in Patent Office: 412 Days
• Field of Search: 438/110, 438/113, 438/106
• US Class Current: 438/110
• CPC Class Codes: B29C 33/0022 Multi-cavity moulds B29C33/301 takes precedence
• CPC Class Codes: B29C 43/36 Moulds for making articles of definite length, i.e. discrete articles
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/0127 Using a carrier for applying a plurality of packaging lids to the system wafer
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H03H 9/0547 consisting of a vertical arrangement H03H9/0566 takes precedence

Abstract

A wafer level hermetically packaged integrated circuit has a protective cover wafer bonded to a semiconductor device substrate wafer. The substrate wafer may contain a cavity. The cover wafer seals integrated circuits and other devices including but not limited to air bridge structures, resonant beams, surface acoustic wave (SAW) devices, trimmable resistors, and micromachines. Some devices, such as SAWs, are formed on the surface of cavities formed in the protective cover wafer. Die are separated to complete the process.

Claims

1. A method for packaging individual die at the wafer level comprising the steps of:

forming a plurality of die in a device substrate, each die comprising at least one device selected from the group consisting of a microelectronic structure, a micromachine, a micromachine component;

forming an insulating layer on a lid wafer comprising a semiconductor layer;

patterning the insulating layer to form a plurality of cavities, each cavity corresponding to one of a different die on the device substrate;

bonding the insulating layer to the device substrate to seal at least one of the devices inside one of the cavities and form a bonded structure of dice covered and sealed inside the corresponding lid cavities.

2. The method of claim 1 wherein the devices are microelectronic structures and further comprising the step of separating the covered dice from each other to form a plurality of separate, packaged integrated circuits.

3. The method of claim 1 further comprising the step of selectively removing the lid wafer semiconductor layer.

4. The method of claim 1 wherein the devices comprise air bridge structures in the device substrate and forming corresponding cavities in the lid wafer to cover the air bridge structures.

5. The method of claim 1 wherein the device and lid wafers are silicon and the insulating layer is silicon dioxide.

6. The method of claim 1 comprising the further step of forming contact openings in the insulating layer and exposing the contact openings when the lid wafer is thinned, and filling the contact opening with metal.

7. The method of claim 6 comprising the further step of forming a plurality of contact pads electrically coupled to the devices, and forming contact openings in the insulating layer aligned with the contact pads.

8. The method of claim 1 comprising the further steps of forming a transparent window in a portion of the lid wafer, aligning the transparent window with cavities in the device wafer, bonding the lid and device wafers and thinning the lid to expose the transparent window.

9. The method of claim 8 wherein the devices comprise laser trimmable resistors in the device substrate.

10. The method of claim 8 wherein the devices comprise resonant beams extending into the cavity.

11. The method of claim 8 wherein the devices comprise photodetectors in the device wafer die.

12. A method for packaging individual die at the wafer level comprising the steps of:

forming a plurality of die in a device substrate, each die comprising at least one device selected from the group consisting of microelectronic structure, micromachines, and micromachinable components;

patterning an insulating lid layer to form a plurality of cover cavities, each cavity corresponding to one of a different die on the device substrate;

bonding the insulating lid layer to the device substrate to seal at least one of the devices inside one of the cavities and form a bonded structure of dies covered by corresponding lid cavities;

removing a portion of the insulating lid layer to provide each die on the device substrate with an individual sealing insulating cover.

13. The method of claim 12 further comprising the steps of patterning the device substrate to have a pattern of scribe streets for separating adjacent dies from each other and patterning the insulating lid layer to have a scribe cavity in a pattern corresponding to the device substrate scribe pattern.

14. The method of claim 13 wherein the insulating lid layer is partially removed by lapping.

15. The method of claim 12 comprising the further step of forming a pattern of conductors on the surface of the cover cavity.

16. The method of claim 12 wherein the insulating lid layer comprises glass.

17. The method of claim 12 wherein the insulating lid layer comprises quartz.

18. A method for packaging individual die at the wafer level comprising:

forming one or more devices in a semiconductor device substrate wafer;

forming one or more electrical bond pads in the semiconductor substrate wafer, spaced from the devices and electrically connected to the device(s) in the semiconductor substrate wafer;

and

sealing and covering the device(s) with a protective cover wafer bonded to the semiconductor device substrate wafer without covering the bond pads.

19. The method of claim 18 comprising the further step of forming a cavity in the semiconductor device substrate wafer for containing a portion of a device.

20. The method of claim 18 wherein the cover wafer is hermetically bonded to the substrate for hermetically enclosing the devices formed in the substrate.

21. The method of claim 18 wherein the cover wafer comprises a material selected from the group consisting of silicon, germanium, silicon germanium, gallium arsenide, glass and quartz.

22. The method of claim 18 wherein the cover wafer comprises a material transparent to a first spectrum of electromagnetic radiation.

23. The method of claim 22 wherein the cover wafer is opaque to a second spectrum of electromagnetic radiation.

24. The method of claim 18 wherein the cover wafer comprises a circuit formed therein.

25. The method of claim 18 wherein the circuit comprises a surface acoustic wave device.

26. The method of claim 18 wherein the cover wafer comprises silicon and portion of the cover wafer is oxidized to form a region of silicon dioxide that is transparent to visible light.

27. The method of claim 18 wherein the protective cover wafer is bonded to the semiconductor substrate wafer by a oxide bonding.

28. The method of claim 18 wherein the protective cover wafer is bonded to the semiconductor substrate wafer by a plastic polymer.

29. The method of claim 28 wherein the plastic polymer is polymethylmethacrylate.

30. The method of claim 18 wherein the protective cover wafer is bonded to the semiconductor substrate wafer by metal seal rings.