Semiconductor device and method of manufacturing the same

• US 5,915,179 A
• Filed: 06/07/1996
• Issued: 06/22/1999
• Est. Priority Date: 06/09/1995
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Tsuchiya, Naofumi, Utsumi, Toshinari, Etou, Hiroki, Ohno, Kazunori, Saito, Takaaki
• Primary Examiner(s): Monin, Jr., Donald L.
• Assistant Examiner(s): DIETRICH, MICHAEL C
• Application Number:
  US08/660,479
• Time in Patent Office: 1,110 Days
• Field of Search: 257/484, 257/342, 257/751, 257/486, 257/766, 438/268, 438/570, 438/582, 438/572
• US Class Current: 438/268
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

In the present invention, a vertical type MOSFET and a Schottky barrier diode which are used as a switching device of a DC--DC converter are formed on the same semiconductor substrate. Further, a barrier metal which is required for the Schottky barrier diode is also formed on an electrode portion of the vertical type MOSFET. In addition, a Schottky barrier diode forming region is formed to have low impurity concentration than a vertical type MOSFET forming region.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming a semiconductor layer having a first conductivity type on a semiconductor substrate having the first conductivity type, said semiconductor layer having an impurity concentration of less than 3×

10¹⁶ /cm³, and a part of said semiconductor layer serving as a drain region;

forming a plurality of base regions having a second conductivity type in said semiconductor layer along a surface thereof;

forming a source region having the first conductivity type in each of said base regions along a surface thereof by diffusing phosphorus or arsenic;

forming a gate insulating layer on said base regions at least between said source region and said drain region;

forming a gate electrode at least on said gate insulating layer;

forming an insulating layer covering said semiconductor layer;

forming a contact hole for a source electrode to expose said source region and said base region, and a contact hole for a Schottky barrier diode to expose a surface of said semiconductor layer by selectively removing said insulating layer;

forming a barrier metal on an entire surface of a resultant structure, forming selectively said barrier metal contacting to both said source region and said base region via said contact hole for said source electrode by patterning said barrier metal, and simultaneously forming said barrier metal contacting to said semiconductor layer via said contact hole for said Schottky barrier diode;

heating an entire resultant structure at a temperature of less than 700°

C. so as to make a Schottky barrier with said barrier metal formed in said contact hole for said Schottky barrier diode and said semiconductor layer; and

depositing aluminum material on said barrier metal and forming an electrode wiring by patterning said aluminum material.

2. A method of manufacturing a semiconductor device comprising the steps of:

forming a semiconductor layer of a first conductivity type on a semiconductor substrate of the first type, said semiconductor layer having an impurity concentration of less than 3×

10¹⁶ /cm³, a part of said semiconductor layer serving as a drain region;

forming a well layer of the first conductivity type having a higher impurity concentration than that of the semiconductor layer on a surface of said semiconductor layer;

forming a plurality of base regions having a second conductivity type in said well layer along thereof by diffusing phosphorus or arsenic;

forming a source region having the first conductivity type in said base regions along a surface thereof;

forming a gate insulating layer on said base regions at least between said source region and said drain region;

forming a gate electrode at least on said gate insulating layer;

forming an insulating layer covering said semiconductor layer;

forming a contact hole for a source electrode to expose said source region and said base region, and a contact hole for a Schottky barrier diode to expose a surface of said semiconductor layer by selectively removing said insulating layer;

forming a barrier metal on an entire surface of a resultant structure, forming selectively said barrier metal contacting to both said source region and said base region via said contact hole for said source electrode by patterning said barrier metal, and simultaneously forming said barrier metal contacting to said semiconductor layer via said contact hole for said Schottky barrier diode;

heating an entire resultant structure at a temperature of less than 700°

C. so as to make a Schottky barrier with said barrier metal formed in said contact hole for said Schottky barrier diode and said one conductivity type semiconductor layer; and

depositing aluminum material on said barrier metal and forming an electrode wiring by patterning said aluminum material.