Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture

• US 5,915,231 A
• Filed: 02/26/1997
• Issued: 06/22/1999
• Est. Priority Date: 02/26/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beffa, Raymond J.
• Primary Examiner(s): ASSOUAD, PATRICK J
• Application Number:
  US08/806,442
• Time in Patent Office: 846 Days
• Field of Search: 702/81, 702/82, 702/83, 702/84, 702/117, 702/118, 702/120, 702/182, 364/468.01, 364/468.17, 364/468.22, 364/468.24, 364/468.28, 438/5, 438/10, 438/14, 438/16, 438/17
• US Class Current: 702/118
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: H01L 21/67294 using identification means, e.g. labels on substrates or labels on containers
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An inventive method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating IC'"'"'s on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad IC'"'"'s on the wafer and the fuse ID'"'"'s of the IC'"'"'s on the wafer. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices. At the opens/shorts test at the end of assembly, the fuse ID of each IC device is automatically retrieved so the wafer map of the IC device may be accessed and evaluated to identify any IC devices containing bad IC'"'"'s that have accidentally been assembled into IC devices. These "bad" IC devices are discarded, and the remaining IC devices continue on to back-end testing.

Claims

1. A method in an integrated circuit (IC) manufacturing process for redirecting one or more IC'"'"'s that have been mis-processed, the IC'"'"'s being of the type to have a substantially unique identification (ID) code, the method comprising:

storing data in association with the ID code of each of the IC'"'"'s that indicates a process flow within the IC manufacturing process that each of the IC'"'"'s should undergo;

reading the ID code of each of the IC'"'"'s;

accessing the data stored in association with the ID code of each of the IC'"'"'s;

evaluating the data accessed for each of the IC'"'"'s to identify any IC'"'"'s that have undergone a process flow within the IC manufacturing process that is different from the process flow their data indicates they should have undergone; and

redirecting any IC'"'"'s identified as having been mis-processed.

2. The method of claim 1 wherein the step of storing data comprises storing the ID code of each of the IC'"'"'s in association with a die location on an electronically stored wafer map.

3. The method of claim 1 wherein the step of storing data comprises storing data at probe.

4. The method of claim 1 wherein the step of storing data comprises storing data in association with the ID code of each of the IC'"'"'s that indicates each of the IC'"'"'s is one of a good IC suitable for assembly and back-end testing and a bad IC suitable for being discarded.

5. The method of claim 1 wherein the step of reading the ID code of each of the IC'"'"'s comprises electrically retrieving a unique fuse ID programmed into each of the IC'"'"'s.

6. The method of claim 1 wherein the step of reading the ID code of each of the IC'"'"'s comprises optically reading a unique ID code provided on each of the IC'"'"'s.

7. The method of claim 6 wherein the step of optically reading a unique ID code provided on each of the IC'"'"'s comprises optically reading a unique laser fuse ID programmed into each of the IC'"'"'s.

8. The method of claim 1 wherein the step of reading the ID code of each of the IC'"'"'s comprises reading the ID code of each of the IC'"'"'s at an opens/shorts test in the IC manufacturing process.

9. The method of claim 1 wherein the step of accessing the data stored in association with the ID code of each of the IC'"'"'s comprises accessing the data stored in association with the ID code of each of the IC'"'"'s at an opens/shorts test in the IC manufacturing process.

10. The method of claim 1 wherein the step of evaluating the data comprises evaluating the data accessed for each of the IC'"'"'s to identify any bad IC'"'"'s that have accidentally undergone an assembly procedure within the IC manufacturing process.

11. The method of claim 1 wherein the step of evaluating the data comprises evaluating the data at an opens/shorts test in the IC manufacturing process.

12. The method of claim 1 wherein the step of redirecting any IC'"'"'s identified as having been mis-processed comprises discarding any IC'"'"'s identified as having been mis-processed.

13. The method of claim 1 wherein the step of redirecting occurs before a back-end test procedure within the IC manufacturing process.

14. The method of claim 1 further comprising assembling the IC'"'"'s into packaged IC devices after the step of storing data and before the step of reading the ID code of each of the IC'"'"'s.

15. A method of manufacturing integrated circuit (IC) devices from semiconductor wafers, the method comprising:

providing a plurality of semiconductor wafers;

fabricating a plurality of IC'"'"'s on each of the wafers;

causing each of the IC'"'"'s on each of the wafers to store a substantially unique identification (ID) code;

storing data in association with the ID code of each of the IC'"'"'s that indicates a manufacturing process flow that each of the IC'"'"'s should undergo;

separating each of the IC'"'"'s on each of the wafers from its wafer to form one of a plurality of IC dice;

assembling each of the IC dice into an IC device;

reading the ID code associated with each of the IC devices;

accessing the data stored in association with the ID code associated with each of the IC devices;

evaluating the data accessed for each of the IC devices to identify any IC devices that have undergone a manufacturing process flow that is different from the manufacturing process flow their data indicates they should have undergone;

redirecting any IC devices identified as having undergone a manufacturing process flow that is different from the manufacturing process flow their data indicates they should have undergone; and

back-end testing any non-redirected IC devices.

16. The method of claim 15 wherein the step of fabricating a plurality of IC'"'"'s on each of the wafers comprises fabricating IC'"'"'s selected from a group comprising Dynamic Random Access Memory (DRAM) IC'"'"'s, Static Random Access Memory (SRAM) IC'"'"'s, Synchronous DRAM (SDRAM) IC'"'"'s, and processor IC'"'"'s.

17. The method of claim 15 wherein the step of causing each of the IC'"'"'s on each of the wafers to store a substantially unique ID code comprises programming each of the IC'"'"'s on each of the wafers to permanently store a unique fuse ID.

18. The method of claim 17 wherein the step of programming each of the IC'"'"'s on each of the wafers to permanently store a unique fuse ID comprises programming at least one of fuses and anti-fuses in each of the IC'"'"'s on each of the wafers to permanently store a unique fuse ID.

19. The method of claim 15 wherein the step of assembling each of the IC dice into an IC device comprises:

picking each of the IC dice from its wafer;

placing each of the IC dice onto an epoxy coated bonding site of one of a plurality of lead frames;

curing the epoxy on the bonding site of each of the lead frames;

wire bonding each of the IC dice to its associated lead frame;

injection molding each of the IC dice and its associated lead frame to form one of a plurality of IC packages each having projecting leads;

de-flashing the projecting leads of each of the IC packages;

curing each of the IC packages;

electroplating the projecting leads of each of the IC packages;

singulating each of the IC packages into one of a plurality of discrete IC devices; and

testing each of the IC devices for opens and shorts.

20. The method of claim 15 wherein the step of assembling each of the IC dice into an IC device comprises assembling each of the IC dice into an IC device selected from a group comprising a wire bond/lead frame IC device, a Chip-On-Board (COB) IC device, a flip-chip IC device, and a Tape-Automated Bonding (TAB) IC device.

21. A method of manufacturing Multi-Chip Modules (MCM'"'"'s) from semiconductor wafers, the method comprising:

providing a plurality of semiconductor wafers;

fabricating a plurality of IC'"'"'s on each of the wafers;

causing each of the IC'"'"'s on each of the wafers to store a substantially unique identification (ID) code;

storing data in association with the ID code of each of the IC'"'"'s that indicates a manufacturing process flow that each of the IC'"'"'s should undergo;

separating each of the IC'"'"'s on each of the wafers from its wafer to form one of a plurality of IC dice;

assembling one or more of the IC dice into each of a plurality of MCM'"'"'s;

reading the ID code of each of the IC dice in each of the MCM'"'"'s;

accessing the data stored in association with the ID code of each of the IC dice in each of the MCM'"'"'s;

evaluating the data accessed for each of the IC dice in each of the MCM'"'"'s to identify any MCM'"'"'s having IC dice that have undergone a manufacturing process flow that is different from the manufacturing process flow their data indicates they should have undergone;

redirecting any MCM'"'"'s identified as having IC dice that have undergone a manufacturing process flow that is different from the manufacturing process flow their data indicates they should have undergone; and

back-end testing any non-redirected MCM'"'"'s.

22. The method of claim 21 wherein the MCM'"'"'s are selected from a group comprising Single In-Line Memory Modules (SIMM'"'"'s) and Dual In-line Memory Modules (DIMM'"'"'s).

23. A method of manufacturing integrated circuit (IC) devices from semiconductor wafers, the method comprising:

providing a plurality of semiconductor wafers;

fabricating a plurality of IC'"'"'s on each of the wafers;

electronically probing each of the IC'"'"'s on each of the wafers to identify good and bad IC'"'"'s on each of the wafers;

programming each of the IC'"'"'s on each of the wafers to store a unique fuse identification (ID);

storing an electronic wafer map for each wafer that identifies the locations of good and bad IC'"'"'s on the wafer and associates each IC on the wafer with its fuse ID;

sawing each of the IC'"'"'s on each of the wafers from its wafer to form one of a plurality of discrete IC dice;

automatically picking each of the IC dice from its wafer;

placing each of the IC dice onto an epoxy coated bonding site of one of a plurality of lead frames;

curing the epoxy on the bonding site of each of the lead frames;

wire bonding each of the IC dice to its associated lead frame;

injection molding each of the IC dice and its associated lead frame to form one of a plurality of IC packages each having projecting leads;

de-flashing the projecting leads of each of the IC packages;

curing each of the IC packages;

electroplating the projecting leads of each of the IC packages;

singulating each of the IC packages into one of a plurality of discrete IC devices;

testing each of the IC devices for opens and shorts;

electrically retrieving the fuse ID associated with each of the IC devices;

accessing the wafer map stored in association with the fuse ID associated with each of the IC devices;

evaluating the wafer map accessed for each of the IC devices to identify any IC devices that include a bad IC and any IC devices that include a good IC;

discarding any IC devices identified as including a bad IC; and

back-end testing any IC devices identified as including a good IC.