Power control apparatus and method for a body implantable medical device

• US 5,916,237 A
• Filed: 04/30/1998
• Issued: 06/29/1999
• Est. Priority Date: 04/30/1998
• Status: Expired due to Fees

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Schu, Carl
• Primary Examiner(s): Kamm, William E.
• Assistant Examiner(s): SCHAETZLE, KENNEDY
• Application Number:
  US09/070,265
• Time in Patent Office: 425 Days
• Field of Search: 607/4, 607/5, 607/2, 607/9, 607/16, 607/59, 607/39, 607/40, 607/42-46, 607/48, 607/50, 607/17, 600/509, 600/522, 600/523
• US Class Current: 607/2
• CPC Class Codes: A61N 1/378 Electrical supply
• CPC Class Codes: A61N 1/39622 Pacing therapy

Abstract

An apparatus and method for controlling power in digital logic circuitry is disposed in a body implantable biomedical device disclosed. A power switch, such as a power gating transistor, is coupled to a digital logic circuit element to selectively control the application of power to the circuit element. During each system clock cycle, power is supplied to the circuit element only for a duration of time required to effect switching of logic states. Power is removed from the circuit element during each system clock cycle when no switching of logic states occurs. A clock signal applied to the gate of a power gating transistor selectively controls the supply of power to the digital circuit logic element during each system clock cycle so as to appreciably reduce static power consumption of the circuit element. The power control apparatus and method may be implemented in any digital logic design, and is well suited for use in digital circuitry that employs combinatorial logic of any complexity and any number of registers or latches. The appreciable reduction in static power consumption realized by employing the power control apparatus and method according to the present invention is particularly useful in digital logic circuitry applications designed to operate at relatively low switching frequencies and low power, such as implantable biomedical device applications.

Claims

1. A body implantable medical apparatus, comprising:

a hermetically sealed housing;

a physiologic transducer coupled to a lead; and

a microprocessor disposed in the housing, the microprocessor coupled to the lead and digital circuitry for controlling operations of the implantable medical apparatus in response to signals generated by the transducer;

the digital circuitry coupled to a power source and a control clock that produces a control clock signal during a period of each cycle of a series of system clock cycles, and the digital circuitry comprising;

a first register circuit;

a second register circuit coupled to the first circuit and receiving power from the power source continuously during each system clock cycle; and

a power switch coupled to the first register circuit and providing power to the first register circuit for a portion of time in response to a first state of the control clock signal, the first register circuit transferring data stored therein to the second register circuit in response to the first state of the control clock signal and the power switch removing power from the first register in response to a second state of the control clock signal;

whereby power is provided to the first register circuit only during the portion of time during each system clock cycle so as to reduce static power consumption of the digital circuitry.

2. The apparatus of claim 1, wherein each of the first and second register circuits comprises one or more transistors and the power switch comprises a power transistor, each of the transistors having a channel length approximately equal to a minimum channel length defined for a particular semiconductor fabrication process, and the power transistor having a channel length that exceeds the minimum channel length defined for the particular semiconductor fabrication process.

3. The apparatus of claim 1, wherein each of the first and second register circuits comprises one or more transistors and the power switch comprises a power transistor, each of the transistors having a channel length approximately equal to a minimum channel length defined for a particular semiconductor fabrication process, and the power transistor having a channel length that exceeds the minimum channel length defined for the particular semiconductor fabrication process by a factor of at least two.

4. The apparatus of claim 1, wherein each of the first and second register circuits comprises one or more transistors and the power switch comprises a power transistor, each of the transistors having a channel length approximately equal to a minimum channel length defined for a particular semiconductor fabrication process, and the power transistor having a channel length that exceeds the minimum channel length defined for the particular semiconductor fabrication process by a factor ranging between approximately one and three.

5. The apparatus of claim 1, wherein each of the first and second register circuits comprises one or more transistors and the power switch comprises a power transistor, each of the transistors having a channel length of less than approximately 0.15 micron, and the power transistor having a channel length of greater than approximately 0.2 micron.

6. The apparatus of claim 1, wherein each of the first and second register circuits comprises one or more transistors and the power switch comprises a power transistor, each of the transistors having a channel length of less than approximately 0.2 micron and the power transistor having a channel length of greater than approximately 0.3 micron.

7. The apparatus of claim 1, wherein the portion of time defines a duration of time one or more magnitudes less than the period of the system clock cycle.

8. The apparatus of claim 1, wherein the portion of time is on the order of nanoseconds, and the period of the system clock cycle is on the order of microseconds.

9. The apparatus of claim 1, wherein the digital circuitry is implemented within the microprocessor.

10. The apparatus of claim 1, wherein the power switch comprises a power gating transistor.

11. The apparatus of claim 1, wherein each of the first and second register circuits comprises one or more transistors and the power switch comprises a power transistor.

12. The apparatus of claim 1, wherein the body implantable medical apparatus is selected from the group consisting of a cardiac pacemaker, pacemaker/cardioverter/defibrillator, nerve stimulator, muscle stimulator, and implantable biomedical monitoring device.

13. A body implantable medical apparatus, comprising:

a hermetically sealed housing;

a physiologic transducer coupled to a lead;

a microprocessor disposed in the housing, the microprocessor coupled to the lead and digital circuitry for controlling operations of the implantable medical apparatus in response to signals generated by the transducer;

the digital circuitry coupled to a power source, a transfer clock, a logic clock, and a latch clock, the transfer clock, logic clock, and latch clock respectively producing a transfer clock signal, latch clock signal, and logic clock signal during each cycle of a series of system clock cycles, and the digital circuitry comprising;

a combinatorial logic circuit;

a first register circuit coupled to the combinatorial logic circuit;

a second register circuit coupled to the first circuit and receiving power from the power source continuously during each system clock cycle;

a first power switch coupled to the combinatorial logic circuit and providing power to the combinatorial logic circuit for a first portion of time in response to a first state of the logic clock signal, the combinatorial logic circuit transferring data to the first register circuit and the first power switch removing power from the combinatorial logic circuit in response to a second state of the logic clock signal; and

a second power switch coupled to the first register circuit and providing power to the first register circuit for a second portion of time in response to a first state of the latch clock signal, the first register circuit transferring data to the second register circuit in response to a state change of the transfer clock signal and the second power switch removing power from the first register circuit in response to a second state of the latch clock signal;

whereby power is provided to the combinatorial logic circuit and the first register circuit only during respective first and second portions of time during each system clock cycle so as to reduce static power consumption of the digital circuitry.

14. The apparatus of claim 13, wherein each of the combinatorial circuit, first register circuit, and second register circuit comprises one or more transistors, and each of the first and second power switches comprises a power transistor, each of the transistors having a channel length approximately equal to a minimum channel length defined for a particular semiconductor fabrication process, and each of the power transistors having a channel length that exceeds the minimum channel length defined for the particular semiconductor fabrication process.

15. The apparatus of claim 13, wherein each of the combinatorial circuit, first register circuit, and second register circuit comprises one or more transistors, and each of the first and second power switches comprises a power transistor, each of the transistors having a channel length approximately equal to a minimum channel length defined for a particular semiconductor fabrication process, and each of the power transistors having a channel length that exceeds the minimum channel length defined for the particular semiconductor fabrication process by a factor ranging between approximately one and three.

16. The apparatus of claim 13, wherein each of the combinatorial circuit, first register circuit, and second register circuit comprises one or more transistors, and each of the first and second power switches comprises a power transistor, each of the transistors having a channel length of less than approximately 0.15 micron, and each of the power transistors having a channel length of greater than approximately 0.2 micron.

17. The apparatus of claim 13, wherein each of the first and second time portions defines duration of time one or more magnitudes less than the period of the system clock cycle.

18. The apparatus of claim 13, wherein each of the first and second time portions is on the order of nanoseconds, and the period of the system clock cycle is on the order of microseconds.

19. The apparatus of claim 13, wherein the first time portion is longer in duration than the second time portion.

20. The apparatus of claim 13, wherein each of the first and second power switches comprises a power gating transistor.

21. The apparatus of claim 13, wherein each of the combinatorial circuit, first register circuit, and second register circuit comprises one or more transistors, and each of the first and second power switches comprises a power transistor.

22. The apparatus of claim 13, wherein each of the combinatorial circuit, first register circuit, and second register circuit comprises one or more transistors, and each of the first and second power switches comprises a power transistor, each of the transistors having a channel length of less than approximately 0.2 micron and each of the power transistors having a channel length of greater than approximately 0.3 micron.

23. The apparatus of claim 13, wherein each of the first and second time portions defines a duration of time less than half of the period of the system clock cycle.

24. The apparatus of claim 13, wherein the first time portion ranges between 100 nanoseconds and 1 microsecond, the second time portion ranges between 50 nanoseconds and 1 microsecond, and the period of the system clock cycle exceeds 100 microseconds.

25. The apparatus of claim 13, wherein the body implantable medical apparatus is selected from the group consisting of a cardiac pacemaker, pacemaker/cardioverter/defibrillator, nerve stimulator, muscle stimulator, and implantable biomedical monitoring device.

26. A method of controlling power provided to digital circuitry disposed in a body implantable medical device, the method comprising:

providing in the body implantable medical device a first register circuit and a second register circuit;

generating system clock signals, each of the system clock signals defining a cycle having an associated period;

providing power to the second register circuit continuously during each system clock cycle;

providing power to the first register circuit and transferring data from the first register circuit to the second register circuit within a portion of time during each system clock cycle, the time portion defining a duration of time less than the period of the system clock cycle; and

removing power from the first register circuit after transferring data from the first register circuit to the second register circuit, whereby power is provided to the first register circuit only during the portion of time during each system clock cycle so as to reduce static power consumption of the digital circuitry disposed in the body implantable medical device.

27. The method of claim 26, wherein:

generating system clock signals comprises generating system clock signals each having a period on the order of microseconds; and

the time portion defines a duration of time on the order of nanoseconds.

28. The method of claim 26, wherein:

generating system clock signals comprises generating system clock signals each having a period of greater than 100 microseconds; and

the time portion defines a duration of time ranging between 10 nanoseconds and 1 microsecond.

29. The method of claim 26, wherein:

generating system clock signals comprises generating system clock signals each having a period of greater than 1 microsecond; and

the time portion defines a duration of time ranging between 10 nanoseconds and 500 nanoseconds.

30. The method of claim 26, wherein the time portion defines a duration of time one or more magnitudes less than the period of the system clock cycle.

31. A method of controlling power provided to digital circuitry disposed in a body implantable medical device, the method comprising:

providing in the body implantable medical device a combinatorial logic circuit and register circuitry, the register circuitry including a master register circuit and a slave register circuit;

generating a system clock signal;

generating, during each cycle of the system clock signal, a latch clock signal, a logic clock signal, and a transfer clock signal;

providing power to the slave register circuit continuously during each system clock cycle;

providing power to the combinatorial logic circuit and propagating data through the combinatorial logic circuit in response to the logic clock signal;

providing power to the master register circuit in response to the latch clock signal;

transferring the data from the combinatorial logic circuit to the master register circuit and then removing power from the combinatorial logic circuit in response to a state change of the logic clock signal;

transferring data from the master register circuit to the slave register circuit in response to the transfer clock signal; and

removing power from the master register circuit in response to a state change of the latch clock signal;

whereby power is provided to the combinatorial logic circuit and the master register circuit only during a respective first and second time portion of each system clock cycle so as to reduce static power consumption of the digital circuitry disposed in the body implantable medical device.

32. The method of claim 31, wherein:

generating system clock signals comprises generating system clock signals each having a period on the order of microseconds; and

each of the first and second time portions defines a duration of time on the order of nanoseconds.

33. The method of claim 31, wherein each of the first and second time portions defines a duration of time one or more magnitudes less than the period of the system clock cycle.

34. A body implantable medical apparatus, comprising:

a hermetically sealed housing;

a first register circuit coupled to a second register circuit, the first and second register circuits disposed in the hermetically sealed housing;

means for generating system clock signals, each of the system clock signals defining a cycle having an associated period;

means for providing power to the second register circuit continuously during each system clock cycle;

means for providing power to the first register circuit and transferring data from the first register circuit to the second register circuit within a portion of time during each system clock cycle, the time portion defining a duration of time less than the period of the system clock cycle; and

means for removing power from the first register circuit after transferring data from the first register circuit to the second register circuit;

whereby power is provided to the first register circuit only during the portion of time during each system clock cycle so as to reduce static power consumption of circuitry disposed in the body implantable medical apparatus.

35. The apparatus of claim 34, wherein:

the generating means comprises means for generating system clock signals each having a period on the order of microseconds; and

the time portion defines a duration of time on the order of nanoseconds.

36. The apparatus of claim 34, wherein:

the generating means comprises means for generating system clock signals each having a period of greater than 1 microsecond; and

the time portion defines a duration of time ranging between 10 nanoseconds and 500 nanoseconds.

37. The apparatus of claim 34, wherein the time portion defines a duration of time one or more magnitudes less than the period of the system clock cycle.

38. The apparatus of claim 34, wherein the body implantable medical apparatus is selected from the group consisting of a cardiac pacemaker, pacemaker/cardioverter/defibrillator, nerve stimulator, muscle stimulator, and implantable biomedical monitoring device.